International Business Machines Corporation

Other

Yun Seog Lee

Devendra K Sadana

Joel Pereira De Souza

Ning Li

Talia S Gershon

Teodor Krassimirov Todorov

Richard Alan Haight

Jeehwan Kim

Stephen W Bedell

Oki Gunawan

Supratik Guha

Douglas M Bishop

Kunal Mukherjee

Saurabh Singh

Arvind Kumar

Babar Ali Khan

Seyoung Kim

Kevin W Brew

Brent A Wacaser

Marinus Hopstaken

Marinus J P Hopstaken

Ravin Mankad

Qinglong Li

Charles Sturdevant

Liang-Yi Chang

Guy M Cohen

Michael S Gordon

Priscilla D Antunez

Yao Yao

Methods of forming a controllable resistive element include forming source and drain regions in a substrate. A battery stack is formed on a substrate between the source and drain regions. Respective anode and cathode electrical connections are formed to the battery stack. Respective source and drain electrical connections are formed.

Battery-based neural network weights

Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.

Semitransparent chalcogen solar cell

A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

Lithium drifted thin film transistors for neuromorphic computing

Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.

Selenium-fullerene heterojunction solar cell

Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.

FinFET resistive switching device having interstitial charged particles for memory and computational applications

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.

Thiourea organic compound for gallium arsenide based optoelectronics surface passivation

A semiconductor structure is provided that contains a non-volatile battery which controls gate bias. The non-volatile battery has a stable voltage and thus the structure may be used in neuromorphic computing. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. In accordance with the present application, the battery stack includes, an anode current collector located on the gate dielectric material, an anode region located on the anode current collector, an ion diffusion barrier material located on the anode region, an electrolyte located on the ion diffusion barrier material, a cathode material located on the electrolyte, and a cathode current collector located on the cathode material.

Battery structure with stable voltage for neuromorphic computing

A controllable resistive element and methods for controlling the resistance of the same include a resistor layer formed in contact with a shared read/write electrode and a read electrode, the resistor layer having a resistivity that depends on a concentration of charge carrier ions. An electrolyte layer is formed on the resistor layer. A reservoir layer is formed on the electrolyte layer and in contact with a write electrode.

High-capacity and high-performance rechargeable batteries containing a cathode material layer having an improved surface roughness is provided. A cathode material layer is provided in which at least an upper portion of the cathode material layer is composed of nanoparticles (i.e., particles having a particle size less than 0.1 &#x3bc;m). In some embodiments, a lower (or base) portion of the cathode material layer is composed of particles whose particle size is greater than the nanoparticles that form the upper portion of the cathode material layer. In other embodiments, the entirety of the cathode material layer is composed of the nanoparticles. In either embodiment, a conformal layer of a dielectric material can be disposed on a topmost surface of the upper portion of the cathode material layer. The presence of the conformal layer of dielectric material can further improve the smoothness of the cathode material layer.

High-capacity rechargeable batteries

Methods for controlling the resistance of a controllable resistive element include determining an amount of electrical resistance change for the controllable resistive element. A concentration difference is determined for a charge carrier ion in a resistor layer of the controllable resistance element that corresponds to the electrical resistance change for the controllable resistive element. A duration and amplitude of a current pulse is determined that changes the charge carrier ion concentration by the determined difference. A positive or negative current pulse is applied to a controllable resistive element for the determined duration.

A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu&#x2014;Zn&#x2014;Sn&#x2014;S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.

Bandgap grading of CZTS solar cell

A solid-state lithium-based battery is provided in which the formation of lithium islands (i.e., lumps) during a charging/recharging cycle is reduced, or even eliminated. Reduction or elimination of lithium islands (i.e., lumps) can be provided by forming a lithium nucleation enhancement liner between a lithium-based solid-state electrolyte layer and a top electrode of a solid-state lithium based battery.

Anode structure for solid-state lithium-based thin-film battery

A controllable resistive element and method of forming the same include a state device configured to provide a voltage-controlled resistance responsive to a voltage input. A dielectric layer is formed directly on the state device. A battery is formed directly on the dielectric layer, configured to apply a voltage to the state device based on a charge stored in the battery. A write device is configured to charge the battery responsive to a write signal. An erase device is configured to discharge the battery responsive to an erase signal.

A photovoltaic device with increased efficiency and a method for making the same. The present invention provides a photovoltaic device including: a transparent substrate; a transparent conductive electrode layer disposed on the transparent substrate; an n-type layer disposed on the transparent conductive electrode layer; a chalcogen absorber layer disposed on the n-type layer; a p-type molybdenum trioxide (MoO3) interlayer disposed on the chalcogen absorber layer; and a conductive layer disposed on the interlayer. A photovoltaic device having a superstrate configuration with the order of the layers reversed is also provided. The present invention further provides methods for making the photovoltaic devices according to the present invention.

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White Plains, NY, United States of America

Yun Seog Lee