United Microelectronics Corp.

Yun-Ren Wang

Ying-Wei Yen

Kuo-Tai Huang

Shu-Yen Chan

Chien-Hua Lung

Chan-Lon Yang

Chien-Liang Lin

Wen-Yi Teng

Chen-Kuo Chiang

Tony E T Liu

Chung-Yih Chen

The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Polysilicon layer and method of forming the same

A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950&#xb0; C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Multi-step annealing process

A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Method of fabricating gate structure

A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping process of the next dose is performed on the dummy wafer. The nitrogen concentration of the chamber is thus adjusted rapidly to switch to the DPN process of the next dose. In addition, after several cycles of the above steps are repeated, a dummy wafer is inserted into the chamber, and a complete DPN process of the next dose is performed on the dummy wafer. This process is performed several times before switching to the next DPN process.

Method for switching decoupled plasma nitridation processes of different doses

A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer is etched back to form spacers on the sidewalls of the gate structure. Finally, a source/drain region is formed in the substrate on each side of the spacer-coated gate structure.

Method of manufacturing metal-oxide-semiconductor transistor

A method for fabricating a dielectric layer doped with nitrogen is provided according to the present invention. According to the method, a dielectric layer is formed on a semiconductor substrate. Two steps of nitridation processes are then performed on the dielectric layer. Following that, one step or two steps of annealing processes are performed on the dielectric layer. Dielectric layer formed by the method has uniform nitrogen dopant, and thus has fine electric properties.

Growing community of inventors

Tainan, Taiwan

Yun-Ren Wang