Samsung Electronics Co., Ltd.

Yun-Rae Cho

Sun-dae Kim

Hyung-gil Baek

Nam-gyu Baek

Sundae Kim

Namgyu Baek

Tae-Hoon Kim

Young-Min Lee

Seokhyun Lee

Seok-Won Lee

Hyunggil Baek

Seunghun Shin

Donghoon Won

Ho-geon Song

Youngmin Lee

Jong-oh Kwon

Kun-dae Yeom

Eunchul Ahn

Nam-Gyu Baek

TaeSung Yoon

A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.

Semiconductor devices having upper and lower solder portions and methods of fabricating the same

Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

Semiconductor device

A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

Substrate, method of sawing substrate, and semiconductor device

Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device

A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.

Semiconductor device having a protection trench, semiconductor wafer including the same, and semiconductor package

The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

Semiconductor devices

Semiconductor devices including guard ring and crack sensing circuit

A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.

Semiconductor chip

Semiconductor device having a peripheral-region defect detection structure

A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion&#x2014;to provide high roughness and firm connection.

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

A semiconductor package that includes a package substrate, a lower semiconductor chip mounted on the package substrate, and an upper semiconductor chip stacked on the lower semiconductor chip in a cascade shape is provided. An active surface of the lower semiconductor chip is facing an active surface of the upper semiconductor chip.

Semiconductor package having cascaded chip stack

A semiconductor package includes a substrate; a first semiconductor chip arranged on the substrate; a second semiconductor chip arranged on the first semiconductor chip; a lead attached to the second semiconductor chip on a side of the second semiconductor chip opposite a side of the second semiconductor chip facing the first semiconductor chip; and a molding member covering an upper surface of the substrate and side surfaces of the lead and sealing the first semiconductor chip and the second semiconductor chip.

Semiconductor package with a lead, package-on-package device including the same, and mobile device including the same

To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Growing community of inventors

Suwon-si, South Korea

Yun-Rae Cho