Micron Technology Incorporated

Yun Li

Kishore Kumar Muchherla

Peter Sean Feeley

Sampath K Ratnam

Ashutosh Malshe

Kevin Roy Brandt

Daniel J Hubbard

Christopher S Hale

Jiangang Wu

John Paul Traver

Ning Zhao

Peng Xu

James P Crowley

Scheheresade Virani

Marc S Hamilton

Violante Moschiano

Michael G Miller

Gary F Besinga

Renato Padilla, Jr

Walter Di-Francesco

Mark Ish

Tom V Geukens

Tom Victor Maria Geukens

Zachary Andrew Pete Vogel

Harini Komandur Elayavalli

Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.

Performance control for a memory sub-system

Methods, systems, and devices for a read counter for quality of service design are described. First commands may be assigned to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level. The memory die may include a second queue associated with a second priority level different from the first priority level, the second queue comprising one or more second commands assigned. Based at least in part on a counter associated with the first queue and the first and second priority levels, it may be determined that a threshold number of the first commands of the first queue have issued without a command from the one or more second commands having issued. A command from the second commands may issue before issuing a next command of the first commands based at least in part on the counter.

Read counter for quality of service design

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Memory device with dynamic cache management

Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

Dynamic selection of cores for processing responses

Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Command batching for a memory sub-system

Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.

Memory die resource management

Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.

Coherency locking schemes

Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.

Internal commands for access operations

System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.

Cache management based on memory device over-provisioning

An example method of generating an execution profile of a firmware module comprises: receiving an execution trace of a firmware module comprising a plurality of executable instructions, wherein the execution trace comprises a plurality of execution trace records, wherein each execution trace record of the plurality of execution trace records indicates a successful execution of an executable instruction identified by a program counter (PC) value; retrieving a first execution trace record of the plurality of execution trace records, wherein the first execution trace record comprises a first PC value; identifying a first executable instruction referenced by the first PC value; identifying a firmware function containing the first executable instruction; incrementing a cycle count for the firmware function by a number of cycles associated with the first executable instruction; and generating, using the cycle count, an execution profile of the firmware module.

Firmware execution profiling and verification

A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.

Power loss data protection in a memory sub-system

Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

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Fremont, CA, United States of America

Yun Li