Samsung Electronics Co., Ltd.

Qualcomm Incorporated

Yun-Ju Kwon

Jin-Ook Song

Dong-Sik Cho

Byung-Tak Lee

Dong-Min Kim

Bo-Rham Lee

Kyung-Chul Yoo

Tae-hong Park

Kang-Min Lee

Yong-chan Kim

Su-Jin Yoon

Ji-Yong Yoon

Myung-chul Cho

Jong-Hyuck Hong

Byeong-Min Lee

Heon-Seok Hong

A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

System on chip controlling memory power using handshake process and operating method thereof

In one embodiment, the integrated circuit includes a clock generator configured to selectively generate a first clock; a processor configured to perform operations; and a clock management circuit. The clock management circuit is configured to receive clock management information from the processor and selectively generate a second clock based on the clock management information and the first clock. The processor is configured to perform some operations based on the second clock.

Clock management unit, integrated circuit including the clock management unit, system on chip, and method of operating the system on chip

An apparatus for a transmit end in a wireless communication system is provided. The apparatus includes at least one scrambler configured to scramble a transmission bit stream, wherein the at least one scrambler comprises, a first circulation unit configured to output, during one cycle, at least one bit for scrambling odd-numbered bits of the transmission bit stream and at least one bit for scrambling even-numbered bits of the transmission bit stream, a second circulation unit configured to output, during one cycle, at least one bit for scrambling odd-numbered bits of the transmission bit stream and at least one bit for scrambling even-numbered bits of the transmission bit stream, and operators configured to generate a scrambled bit stream, wherein each of the operators generates a scrambled bit using an input bit, an output bit from the first circulation unit and an output bit from the second circulation unit.

Apparatus and method for scrambling in a wireless communication system

An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller.

Apparatus and method for adaptive frequency scaling in digital system

An apparatus and method for automatically controlling a gain in a portable communication system are provided. The apparatus includes a channel determiner for controlling a fading margin depending on the channel variation amount to control the limited total dynamic range of the ADC.

Apparatus and method for automatically controlling gain in portable communication system

An apparatus and method for scrambling in a wireless communication system are provided. The apparatus includes a selector, a plurality of scramblers, and a plurality of modulators. The selector selects a scrambling scheme to be applied to a transmission bit stream according to a modulation scheme to be applied to the transmission bit stream. The plurality of scramblers scramble the transmission bit stream according to a scrambling scheme corresponding to each of a plurality of modulation schemes. The plurality of modulators modulate the scrambled transmission bit stream according to the plurality of modulation schemes.

An apparatus and for preventing a glitch in a clock switching circuit includes a select signal manager and a clock gate unit. The select signal manager generates a detect change signal, provides the detect change signal as an input signal for generating a clock gate signal to the clock gate unit, and changes a muxsel signal into a select signal using the clock gate signal to select a clock intending for switching. Upon receiving the detect change signal, the clock gate unit gates a received clock, generates the clock gate signal using a level of the detect change signal as an input signal, and provides the generated clock gate signal to the select signal manager.

Apparatus and method for preventing generation of glitch in a clock switching circuit

Disclosed is a method for detecting a frequency offset in an Orthogonal Frequency Division Multiplexing (OFDM) system. The method includes determining a first frequency index based on autocorrelation values calculated according to a frequency index for a pilot signal of a received symbol, accumulating the autocorrelation values calculated according to the frequency index for the pilot signal of the received symbol depending on a symbol count, and determining a second frequency index based on the accumulated autocorrelation values, and determining at least one of the first frequency index and the second frequency as a frequency offset according to channel quality.

Growing community of inventors

Suwon-si, South Korea

Yun-Ju Kwon