Samsung Electronics Co., Ltd.

Yun-Jae Lee

Min-Hee Lee

Jae-Hoon Kim

Se-Chung Oh

Jeong-Heon Park

Woo-Jin Kim

Hee-Ju Shin

Joon-Myoung Lee

Han-Gyul Kim

Sung-Min Kim

Jae-Man Yoon

Chang-Hwan Kim

Sang-hyun Lee

Se-Myeong Jang

Kyu-Hyun Lee

Man-Jong Yu

Won-Seong Lee

Min-sung Kang

Hyeon-Kyu Lee

Myoung-Hee Han

Ki-Woong Kim

Joon-Mo Kwon

Wook-je Kim

Ki-woong Kim

Won-Mo Park

Jeong-hoon Oh

Kwang-Youl Chun

Sei-lyn Kwak

Seung-Beom Kim

An electronic device and a method for reproducing a sound in the electronic device are provided. The electronic device includes a touchscreen displaying a keyboard having a plurality of keys and a plurality of sound source buttons corresponding respectively to a plurality of different sound sources, a processor connected electrically to the touchscreen, and a memory connected electrically to the processor, wherein the memory stores instructions that are executed to cause the processor to perform control such that when an input to at least one key among the plurality of keys is received, the sound source corresponding to at least one sound source button selected among the plurality of sound source buttons is reproduced as a sound corresponding to the received input.

Electronic device and method for reproducing sound in the electronic device

A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Semiconductor device having pinned layer with enhanced thermal endurance

Display screen or portion thereof with graphical user interface

A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.

Semiconductor device having isolation region

Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.

Method of forming a reliable high performance capacitor using an isotropic etching process

A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

Method for fabricating semiconductor device with self-aligned storage node

The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.

Method of processing a defect source at a wafer edge region in a semiconductor manufacturing

A method of fabricating semiconductor device, which reduces amount of oxidization on semiconductor substrate to suppress volume expansion of an active region of a semiconductor substrate, thereby removing pits on the semiconductor substrate. A conductive layer for forming a gate electrode and a first insulating layer serving as a mask are sequentially formed on the semiconductor substrate. Using a mask for forming a gate electrode, the first insulating layer and the conductive layer are sequentially etched to form a gate electrode. A second insulating layer and a third insulating layer are formed on the structure of the gate electrode and the surface of the semiconductor substrate. A third insulating layer formed on an overall surface of the semiconductor substrate is dry etched to form an insulating layer spacer on sidewalls of the gate electrode. A fourth insulating layer is formed on the structure of the semiconductor substrate and the gate electrode by a deposition process. That is, after forming an insulating layer spacer on sidewalls of the gate electrode, an oxide layer is formed by a deposition process so as to compensate for damage.

Method of fabricating a semiconductor device

Growing community of inventors

Seoul, South Korea

Yun-Jae Lee