Skhynix Inc.

Hynix Semiconductor Inc.

Yun-Hyuck Ji

Seung-Mi Lee

Se-Aug Jang

Beom-Yong Kim

Woo-Young Park

Hyung-Chul Kim

Beom-Ho Mun

In-Sang Kim

Tae-Yoon Kim

Kwan-Woo Do

Moon-Sig Joo

Tae-Kyun Kim

Kee-Jeung Lee

Jin-Yul Lee

Kyung-Woong Park

Bong-Seok Jeon

Ji-Hoon Ahn

Jae-Hyoung Koo

A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.

Semiconductor device having low-k spacer and converting spacer and method for fabricating the same

A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.

Semiconductor device including ultra low-k spacer and method for fabricating the same

Semiconductor device having low-k spacer and method for fabricating the same

A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.

Transistor, method for fabricating the same, and electronic device including the same

A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

Semiconductor device with metal gate and high-k dielectric layer, CMOS integrated circuit, and method for fabricating the same

A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.

Semiconductor device including gate structure for threshold voltage modulation in transistors and method for fabricating the same

A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.

Transistor including a stressed channel, a method for fabricating the same, and an electronic device including the same

A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.

Semiconductor device having buried bit line and method for fabricating the same

A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.

Method and gate structure for threshold voltage modulation in transistors

A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.

Semiconductor device with metal gate and high-k materials and method for fabricating the same

A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.

Method of forming gate dielectric layer and method of fabricating semiconductor device

A method for fabricating a semiconductor device includes: forming a gate dielectric layer over a substrate; forming an etch stop layer over the gate dielectric layer; forming a first work function layer that covers a first portion of the etch stop layer and a sacrificial compound that covers a second portion of the etch stop layer; exposing the second portion of the etch stop layer by removing the sacrificial compound; and forming a second work function layer over the second portion of the etch stop layer and the first work function layer.

Growing community of inventors

Gyeonggi-do, South Korea

Yun-Hyuck Ji