Samsung Electro-mechanics Co., Ltd.

Yun Hwi Park

Tae Soo Lee

Yun Hee Cho

Ji Hoon Kim

Taek Jung Lee

Beom Joon Cho

Chul Soon Park

Jong Myeon Lee

Won Hee Yoo

Byeung Gyu Chang

Yoon Hyuck Choi

Bong Gyun Kim

Disclosed herein are a thin film electrode ceramic substrate and a method for manufacturing the same. The thin film electrode ceramic substrate includes: a ceramic substrate; one or more anti-etching metal layers formed in a surface of the ceramic substrate; thin film electrode pattern formed on the anti-etching metal layers; and a plating layer formed on the thin film electrode pattern, wherein respective edge portions of the thin film electrode pattern are contacted with the anti-etching metal layer, and thus, an undercut defect occurring between the surface of the ceramic substrate and the thin film electrode pattern and between the thin film electrode patterns due to an etchant can be prevented and the binding strength of the entire thin film electrode pattern can be enhanced, resulting in securing durability and reliability of the thin film electrode patterns.

Thin film electrode ceramic substrate and method for manufacturing the same

There is provided a Low Temperature Co-fired Ceramic (LTCC) composition, an LTCC substrate comprising the same, and a method of manufacturing the same. The LTCC composition includes 20 to 70 parts by weight of ceramic powder; and 30 to 80 parts by weight of glass component for low-temperature sintering, wherein the ceramic powder has plate-shaped ceramic powder particles and globular ceramic powder particles, and the ceramic powder has a content ratio of the globular ceramic powder particles with respect to the plate-shaped ceramic powder particles in a range of 0 to 1.

LTCC composition, LTCC substrate comprising the same and method of manufacturing the same

There is provided a multilayer ceramic substrate including a conductive via of a dual-layer structure capable of preventing loss in electrical conductivity and signal. The multilayer ceramic substrate includes: a plurality of dielectric layers; and a circuit pattern part formed on at least a portion of the dielectric layers, the circuit pattern part including at least one conductive via and conductive pattern, wherein the at least one conductive via comprises an outer peripheral portion and an inner peripheral portion, the outer peripheral portion formed along an inner wall of a via hole extending through the dielectric layers and formed of a first conductive material containing a metal, and the inner peripheral portion filled in the outer peripheral portion and formed of a second conductive material having a shrinkage initiation temperature higher than a shrinkage initiation temperature of the first conductive material.

Multilayer ceramic substrate

In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.

Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole

Provided is an electron chip module having a heat sink that can increase heat dissipation efficiency. A bottom surface of a module circuit board and an upper surface of a heat sink are in direct contact with each other by using a metal wire, such that heat generated during the operation of a heat-generating device chip mounted onto the module circuit board can be effectively dissipated to the outside.

Electronic chip module

A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

Semiconductor chip package

There is provided a power amplifying device having a linearizer in which a bias circuit has an initial impedance set when initially operated, then the impedance is varied according to a level of an input signal and the input signal is amplified in a broad range from a low level region to a high level region, thereby improving linearity of an output signal. The power amplifying device including: an amplifying unit receiving a bias power source and amplifying an input signal; a bias unit varying the bias power source according to a set impedance to provide to the amplifying unit; and an impedance setting unit setting the impedance of the bias unit in response to a preset control voltage when the bias unit is initially operated and re-setting the impedance of the bias unit according to a level of the input signal of the amplifying unit after initial operation of the bias unit.

Power amplifying device having linearizer

There is provided a multi-layered band pass filter capable of improving a stop characteristic out of a pass band and reducing the entire size of the filter. The multi-layered band pass filter includes a ceramic laminated body having at least first to fifth dielectric layers laminated sequentially therein; first and second resonators having symmetrical patterns of first and second inductors formed on the first dielectric layer, and symmetrical patterns of first and second capacitors formed on the second dielectric layer so that they are at least partially overlapped with the patterns of the first and second inductors; a pattern of first and second load capacitors electrically capacitively coupled respectively to ends of the first and second resonators formed on the third dielectric layer; a pattern of first and second notching capacitors electrically capacitively coupled respectively to the other ends of the first and second resonators formed on the third dielectric layer; and first and second ground planes formed respectively on the fourth and fifth dielectric layers, wherein each of the patterns of the first and second inductors is composed of a low impedance portion formed of wide-width lines and a high impedance portion formed of meander-type narrow-width lines from the low impedance portion.

Growing community of inventors

Gyunggi-do, South Korea

Yun Hwi Park