Samsung Electronics Co., Ltd.

Yun-Ho Youm

Hong-mook Choi

Jae-Chul Park

Jaechul Park

Hye-Soo Lee

Jin-su Hyun

Heon-Soo Lee

Hyesoo Lee

Tong-Pyo Hong

Kyung-Ae Kim

Sang-Hyun Park

Yong Ki Lee

Mi-jung Noh

Jong-hoon Shin

Heonsoo Lee

Yong-ki Lee

KeeMoon Chun

Young-jin Chung

Mijung Noh

Hye-soo Lee

Xingguang Feng

Jinsu Hyun

Kyungae Kim

Ki-Seok Bae

Hong-Mook Choi

TongPyo Hong

A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Security devices, electronic devices and methods of operating electronic devices

An electronic circuit includes an operator including logic gates configured to perform either one or both of encryption and decryption operations. The electronic circuit further includes a controller configured to control the operator to operate in a first mode in which each of the logic gates outputs a first logic value during a first time period of a clock signal, and operate in a second mode in which a number of first logic gates, each of which outputs the first logic value, among the logic gates, and a number of second logic gates, each of which outputs a second logic value, among the logic gates, are maintained constant during a second time period of the clock signal, in response to a control value indicating that either one or both of the encryption and decryption operations are performed.

Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same

Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.

Electronic system having integrity verification device

An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.

Endecryptor preventing side channel attack, driving method thereof and control device having the same

A system on chip includes a central processing unit and a key manager coupled to the central processing unit. The key manager includes a random number generator configured to generate a key and a key memory configured to store the key and a user setting value associated with the key.

Processors including key management circuits and methods of operating key management circuits

A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Encoder and method for encoding thereof

An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.

Semiconductor device having multi access level and access control method thereof

In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

Apparatus and method of authenticating joint test action group (JTAG)

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Seoul, South Korea

Yun-Ho Youm