Samsung Electronics Co., Ltd.

Yun-Ho Choi

Seung-Hun Lee

Churoo Park

Hyun-Soon Jang

Ho-cheol Lee

Tae-jin Kim

Si-Yeol Lee

Myung-Ho Kim

Chull-Soo Kim

Soo-In Cho

Dae-je Chin

Ejaz Ul Haq

Nam-Soo Kang

Seung-Moon Yoo

Jin-Gi Hong

Jung-Hun Seo

Jin-ho Kim

Seung-hun Lee

Su-hyun Nam

Eun-Taeck Lee

Kyung-Bum Koo

In-Young Park

Sung-Sok Choi

Hyun Chul Kwun

Hyun-Chul Kwun

Eui-Jin Park

Hwan-Il Jeong

Jun-Bum Shin

Hyun-Kwon Chung

Yong-Kuk You

Su-Hyun Nam

Disclosed are chamber inserts and apparatuses using the chamber inserts. A chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, a first protruding portion extending outwardly from a first portion of the cylindrical body portion, the first portion positioned circumferentially along the cylindrical body portion and a second protruding portion extending outwardly from a second portion of the cylindrical body portion, the second portion positioned circumferentially along less than all of the cylindrical body portion. In another example, the chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, the cylindrical body portion including a slit and at least one hole, the slit and the at least one hole positioned circumferentially along the cylindrical body portion and a first protruding portion extending outwardly from a first portion of the cylindrical body portion.

Chamber inserts and apparatuses for processing a substrate

In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.

Method of forming a layer and method of removing reaction by-products

Plasma processing equipment having a structure for preventing gap formation includes: a chamber inside which a plasma environment is formed; an upper electrode positioned at a upper position of the chamber; an electrostatic chuck positioned at a lower position of the electrostatic chuck, having a lower electrode and holding a wafer on a top surface thereof; a ring positioned at an outer side of the electrostatic chuck; and a gap prevention unit for isolating from the outside a space between the electrostatic chuck and the ring.

Structure for preventing gap formation and plasma processing equipment having the same

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Multi-bank dynamic random access memory devices having all bank precharge capability

A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Semiconductor memory device

Circuit in a semiconductor memory for programming operation modes of the

Synchronous dram having a plurality of latency modes

System for selecting one of a plurality of memory banks for use in an

Semiconductor memory having a plurality of I/O buses

A burn-in enable circuit and burn-in test method of a semiconductor memory device are disclosed. A high voltage exceeding the external power voltage by a predetermined amount is applied to at least one of a plurality of pins normally used with a connected semiconductor memory chip to initiate a burn-in test mode. The burn-in test enable circuit senses this high voltage and causes the reset operation of word lines in the chip to become disabled. This allows for a high stress voltage to be applied to all access transistors in the chip simultaneously during a burn-in test for substantially the same amount of time. Therefore, burn-in time is substantially reduced and a reliable burn-in test is obtained.

Burn-in circuit and burn-in test method

A semiconductor memory device using a clock of a constant period supplied from the exterior of a memory chip and a sense amplifier for reading out data from a memory cell designated by an address includes at least two different delay circuits for setting at least two delay time periods from the clock, a selecting circuit for receiving signals generated from the delay circuits and selecting one of said signals by a given control signal, and a data output buffer for receiving the data generated from the sense amplifier by a signal generated from the selecting circuit.

Data output buffer of a semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.

Semiconductor memory device having a plurality of row address strobe

A sense amplifier of a semiconductor memory device for performing a high-speed sensing operation. A sensing node SAN and SAN of the sense amplifier is precharged to a power voltage level and during a sensing operation, first and second clock signals which are shifted to the power voltage and a ground voltage level, respectively, are applied to the sense amplifier. Thus, a potential difference of the sensing node dependent on a precharge state of the power voltage level is generated quickly and sufficiently. Therefore, the high speed sensing operation and a fast access of data can be performed, thereby improving the performance of the semiconductor memory device.

Sense amplifier for performing a high-speed sensing operation

Growing community of inventors

Suwon, South Korea

Yun-Ho Choi