Samsung Display Co., Ltd.

Yun Hee Kwak

Bon-Yong Koo

Mi-Sun Lee

Jeong Min Park

Sung Chul Hong

Jong Woong Jang

Jae Ho Choi

Ho-Kyoon Kwon

Jong Woong Chang

Joo-Yeon Won

Sung-dong Park

Ho Kyoon Kwon

Young Jae Jeon

Hyoung-Joon Kim

Dong Yeon Son

Chong Guk Lee

Byung Goo Jung

Kyung Hyun Kim

Kyung Hee Kim

A liquid crystal display, including: a liquid crystal panel; and a visual inspection unit positioned in an outer region of the liquid crystal panel and transferring a test signal to the liquid crystal panel, in which the visual inspection unit includes: a test pad to which a test signal is applied; a first test line connected to the test pad; and a second test line connected to the test pad through a bridge line.

Liquid crystal display

A display device includes: a first display panel including: a display area including a first edge, a second edge and a third edge, where the first and second edges are disposed opposite to each other, and the third edge is connected to the first and second edges, a peripheral area around the display area, and a plurality of pixels disposed in the display area; a first common voltage transmitting line extending along the third edge, where the first common voltage transmitting line transmits a first common voltage to the display area through a plurality of input points sequentially disposed along the third edge; and a second common voltage transmitting line extending along the third edge, where the second common voltage transmitting line transmits a second common voltage to the display area through a supplementary input point, which is adjacent to the second edge or the third edge.

Display device

A display device including a display panel including a chip mounting region and a driver mounted on the chip mounting region, the driver configured to provide signals to a display region of the display device to display an image on the display region. The display panel includes a first connection line, a second connection wire line, and a third connection wire line sequentially disposed in the chip mounting region; a first shorting bar, a second shorting bar, and a third shorting bar correspondingly connected to the first connection wire line, the second connection wire line, and the third connection wire line; and a bridge wire line configured to electrically connect at least one of the first, second, and third shorting bars and the second connection wire line. Neighboring connection wire lines of the first, second, and third connection wire lines are disposed in different layers.

Provided is a display device including a plurality of pixels; a plurality of data lines connected to the plurality of pixels; a data driver applying data voltages to the plurality of data lines; and a first test pad unit connected to at least one of the plurality of data lines in order to check the data voltages, in which the first test pad unit includes a test pad which is electrically double-separated from the at least one of the data lines.

A thin film transistor array panel is capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain electrode by reducing an area of a thin film transistor. The thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer on the gate line; a semiconductive island on the gate insulating layer; a circular drain electrode on the semiconductive island; and a source electrode disposed on the semiconductive island and shaped like a circular band bent in a direction from which the drain electrode is disposed. The gate electrode may include a circular portion that is overlapped by the drain electrode and a circular sector portion that is overlapped by the source electrode.

Thin film transistor array panel

A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.

A thin film transistor substrate includes: first and second driving chips; a plurality of signal lines respectively connected to the first and second driving chips; a plurality of first and second branch repair lines extended across the plurality of signal lines connected to the first driving chip; a plurality of third and fourth branch repair lines extended across the plurality of signal lines connected to the second driving chip; an insulating layer between the plurality of first and second branch repair lines and the plurality of signal lines connected to the first driving chip, and between the plurality of third and fourth branch repair lines and the plurality of signal lines connected to the second driving chip; a first repair line connecting the first and second branch repair lines to each other; and a second repair line connecting the third and fourth branch repair lines to each other.

Thin film transistor substrate and liquid crystal display including the same

A liquid crystal display includes a first substrate, a second substrate, a first sealant, a second sealant, and a gate driving circuit portion. The second substrate faces the first substrate. The first substrate and the second substrate have a display area and a peripheral area peripherally about the display area. The second sealant is spaced apart from the first sealant. The second sealant is disposed in the peripheral area. The gate driving circuit portion is disposed on the first substrate and between the first sealant and the second sealant.

Liquid crystal display including circuitry between sealants

A liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of pixel areas, a plurality of spacers maintaining a distance between a first display panel and a second display panel, an insulating layer formed on the first display panel, and a plurality of contact holes formed in the insulating layer, and each contact hole connecting an upper conductive layer with a lower conductive layer, in which the pixel areas include a first pixel area group of pixel areas having the contact holes and a second pixel area group of pixel areas not including the contact holes, and the spacers are positioned in respective pixel areas of the second pixel area group and disposed at portions corresponding to where the contact holes are positioned in the pixel areas of the first pixel area group.

Growing community of inventors

Hwaseong-si, South Korea

Yun Hee Kwak