Intel Corporation

Yun He

Sanjib Sarkar

Narender R Nagulapally

Fei Deng

Senthil Arun Singaravelu

Pranali Shah

Adhiveeraraghavan Srikanth

Ivan Herrera Mejia

Ruchira K Liyanage

In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

Jitter sensing and adaptive control of parameters of clock and data recovery circuits

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

Unequalized clock data recovery for serial I/O receiver

Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.

Adaptive backchannel equalization

Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.

Growing community of inventors

Santa Clara, CA, United States of America

Yun He