Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Yun-Han Lee

Sandeep Kumar Goel

Ankita Patidar

William Wu Shen

Marat Gershoig

Tze-Chiang Huang

Kai-Yuan Ting

Chewn-Pu Jou

Yen-Huei Chen

Hung-Jen Liao

Lee-Chung Lu

Huan-Neng Chen

Hidehiro Fujiwara

Jonathan Tsung-Yung Chang

Feng Wei Kuo

Lan-Chou Cho

Jack Liu

Huang-Yu Chen

Hong-Chen Cheng

Yi-Lin Chuang

Hsien-Hsin Sean Lee

Saman M I Adham

Ravi Venugopalan

Saman Mi Adham

A non-transitory computer-readable storage medium is encoded with a set of instructions for designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications that, when executed by at least one processor, cause the at least one processor to: retrieve a source code operable to execute a plurality of operations of a machine learning algorithm; classify a first group of the plurality of operations as slow group operations and classify a second group of the plurality of operations as fast group operations, based on a time required to complete each operation; define a neural network operable to execute the slow group operations; define a trained neural network configuration including a plurality of interconnected neurons operable to execute the slow group operations; and generate an ESL platform for evaluating a design of a semiconductor device based on the trained neural network configuration.

System and method for ESL modeling of machine learning

A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit that includes a set of circuit blocks or a first set of heaters. The integrated circuit design corresponding to the integrated circuit. The performing the simulation includes determining a heat signature of the integrated circuit design from configured power information or location information for each circuit block of the set of circuit blocks or each heater of the set of heaters included in the integrated circuit design. The heat signature includes heat values distributed throughout the integrated circuit design.

Method of testing an integrated circuit and testing system

In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

Scan architecture for interconnect testing in 3D integrated circuits

A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.

Network-on-chip system and a method of generating the same

A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

Circuit and methodology for power profile

A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

Integrated circuit design method, system and computer program product

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Integrated circuit die with memory macro including through-silicon via and method of forming the same

A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

Method and system for reducing migration errors

An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Integrated circuit with radio frequency interconnect

A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

Memory circuit and cache circuit configuration

A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

Cell layout of semiconductor device

A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group and/or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing the slow operation group operation on the machine learning hardware configuration, finalizing the machine learning hardware configuration capable of successfully executing least one test data set.

Growing community of inventors

Hsinchu, Taiwan

Yun-Han Lee