Samsung Electronics Co., Ltd.

Yun-Gi Kim

Dong-Gun Park

Choong-Ho Lee

Gyo-young Jin

Sung-Sam Lee

Byung-yong Choi

Hye-jin Cho

Young-mi Lee

Bong-Soo Kim

Yong-Tae Kim

Dae-Won Ha

Seong-goo Kim

Jong-woo Park

Hyeoung-Won Seo

Mi-Youn Kim

Sang-Ho Kim

Ki-Nam Kim

Jae-Man Yoon

Jin-wook Lee

Dong-kyun Kim

Kang-yoon Lee

Jae-sik Min

Byung-ha Park

Doo-youl Lee

Myung-jong Kwon

Young-Woong Son

Hwa-Young Ko

Jong-Woo Park

Young-shik Park

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

Methods of fabricating semiconductor devices having buried word line interconnects

A solar cell is provided with a semiconductor substrate including a light-receiving surface, a back surface, a first region of a first conductivity type disposed on the back surface, a second region of a second conductivity type disposed on the light-receiving surface, and a PN junction at the boundary between the first and second regions. An electrode is provided on the light-receiving surface to expose a portion of the light-receiving surface, and the semiconductor substrate includes a plurality of recesses formed by recessing the exposed portion of the light-receiving surface. The recesses may function as a texturing structure.

Solar cells and methods of forming the same

A method of manufacturing a solar cell includes providing a semiconductor substrate; disposing a reflection layer on one side of the semiconductor substrate, wherein the disposing the reflection layer comprises implanting gas into a surface of the one side of the semiconductor substrate and heating the gas; disposing an n+ region and a p+ region separated from each other on the other opposite facing side of the semiconductor substrate; disposing a first electrode connected to the n+ region; and disposing a second electrode connected to the p+ region.

Method of manufacturing solar cell

Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.

Methods of forming semiconductor solar cells having front surface electrodes

A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Non-volatile memory device for 2-bit operation and method of fabricating the same

An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

Integrated circuit wire patterns including integral plug portions

In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void

An ink-jet printhead and a method of manufacturing the same include a substrate on which a heater and a passivation layer protecting the heater are formed, a passage plate on which an ink chamber corresponding to the heater and an ink passage connected to the ink chamber are formed, and a nozzle plate in which an orifice corresponding to the ink chamber is formed. An exposure stop layer (ESL) that blocks passage of a photosensitive energy is formed inside the nozzle plate, and the nozzle plate and the passage plate are bonded with each other by the exposure stop layer (ESL).

Monolithic ink-jet printhead and method of manufacturing the same

A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Semiconductor device and method of manufacturing the same

Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

Transistors, semiconductor integrated circuit interconnections and methods of forming the same

A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

Vertical type nanotube semiconductor device

Method of manufacturing a semiconductor device having a switching function

An ink-jet printhead, and a method for manufacturing the same. The printhead includes a substrate, a first insulating layer on the surface of the substrate, first and second conductors on the first insulating layer separated from each other, a heater including conductor connection layers for electrically connecting the first and second conductors to each other and between the first and second conductors. A second insulating layer is between the first and second conductors and between the conductor connection layers, and a barrier wall is provided on the substrate and defines an ink chamber filled with ink to be ejected. A nozzle plate is provided on the barrier wall, and forms upper walls of the ink chamber and in which nozzles, through which ink filled in the ink chamber is ejected, are formed.

Growing community of inventors

Gyeonggi-do, South Korea

Yun-Gi Kim