Samsung Electronics Co., Ltd.

Skhynix Inc.

Yun-Gi Hong

Bong-Uk Lim

Gyeong-sun Park

Jun-Won Bae

Seok-Won Bae

Kyong-Hwan Kim

Hee-Yul Kim

Son-Young Lee

Ji-Sang Park

Min-Hyoug Boo

Byeong-Yong Song

Hoon-Tae Kim

Kwang-soo Ha

Joon-Seok Kang

Chung-Ha Kim

Jong-Kyu Kim

Jun-won Bae

Tae-Kung Park

Min-Hyoung Boo

Gisuke Ota

An operating method of a memory device includes: instructing, by a master chip, a first memory chip and a second memory chip to perform a read operation; transferring, by the first memory chip, data stored in the first memory chip to the master chip through a first through-chip channel in response to the read operation instruction, and transferring, by the second memory chip, data stored in the second memory chip to the master chip through a second through-chip channel in response to the read operation instruction; comparing, by the master chip, a phase of the data transferred through the first through-chip channel with a phase of the data transferred through the second through-chip channel; and adjusting a delay value of a data transmission channel of at least one of the first memory chip and the second memory chip based on a result of the comparing.

Memory device including memory chips and operation method thereof

A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.

Semiconductor memory device and operating method thereof

A signal transmitting circuit includes a signal driving unit suitable for driving an output signal in response to an input signal, during an operation mode, and a level shifting unit suitable for shifting a logic level of the output signal in a predetermined cycle, during a standby mode.

Memory device and signal transmitting circuit thereof

A pipe latch circuit includes: a pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.

Pipe latch circuit which controls output of data in a read operation and data output circuit including the same

A semiconductor memory device includes a memory cell array; a memory cell array; a data receiver suitable for receiving a plurality of data sequentially inputted from an exterior, the plurality of data including previous data and current data; a data driving controller suitable for detecting the number of toggling values of the current data in comparison with the previous data and generating first to fourth driving control signals based on the number of toggling values; and a driver suitable for receiving input data through the data receiver and driving the input data or inverted input data to data transfer lines in response to the first to fourth driving control signals.

Growing community of inventors

Kyunggi-do, South Korea

Yun-Gi Hong