Taiwan Semiconductor Manufacturing Comp. Ltd.

Yun-Feng Kao

Katherine H Chiang

Ming-Yen Chuang

Chien-Hao Huang

Gao-Ming Wu

Chung-Te Lin

Chia-En Huang

Sheng-Chih Lai

Wei Ju Lee

Chen-Jun Wu

Wai-Kit Lee

Jyun-Yan Kuo

A memory device includes a plurality of memory cells. Each of the plurality of memory cells includes a capacitor configured to store an amount of electrical charges, and a plurality of transistors electrically coupled to the capacitor. Based on a pulse signal, a first subset of the plurality of transistors are configured to form a first conduction path, and a second subset of the plurality of transistors are configured to form a second conduction path. The amount of electrical charges is configured to be altered through the first conduction path and the second conduction path.

Back-end-of-line memory devices and methods for operating the same

A semiconductor device structure providing a NOT gate logic function includes a layer stack including a pair of semiconductor layers having opposite conductivity-types, and a dielectric isolation layer disposed therebetween. First and second electrodes are located on a first side of the layer stack, where the first electrode contacts a first side surface of a first semiconductor layer and a second electrode contacts a first side surface a second semiconductor layer. A third electrode located on a second side of the layer stack contacts a second side surface of the first semiconductor layer and a second side surface of the second semiconductor layer. A gate dielectric layer is located over two side surfaces of the layer stack. A pair of gate electrodes located on either side of the layer stack contacts the gate dielectric layer. The semiconductor device structure may be fabricated using a BEOL process using metal-oxide semiconductor materials.

Back-end-of-line semiconductor device structure providing a not-gate logic function and methods of forming the same

An embodiment inverter circuit may include a gate electrode formed over an interlayer dielectric layer, a gate dielectric layer formed over the gate electrode, a first-conductivity-type semiconductor layer formed over the gate dielectric layer, a second-conductivity-type semiconductor layer formed over the gate dielectric layer and laterally displaced from the first-conductivity-type semiconductor layer, a first source electrode formed in contact with the first-conductivity-type semiconductor layer, a second source electrode formed in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode formed in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer may include a metal-oxide semiconductor and/or a multi-layer structure formed in a back-end-of-line (BEOL) process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.

Back-end-of-line CMOS inverter having reduced size and reduced short-channel effects and methods of forming the same

A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.

Capacitor structure and method of making the same

Various embodiments of the present application are directed towards a memory device including a memory cell. The memory cell includes a plurality of semiconductor devices disposed on a substrate. A lower inter-metal dielectric (IMD) structure overlies the semiconductor devices. A plurality of conductive vias and a plurality of conductive wires are disposed within the IMD structure and are electrically coupled to the semiconductor devices. A data backup unit overlies the plurality of conductive vias and wires. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer, a first memory gate structure, and a second memory gate structure. The first and second memory gate structures include an upper gate electrode over a ferroelectric layer. The first and second source/drain structures are directly electrically coupled to the semiconductor devices by way of the conductive vias and wires.

Data backup unit for static random-access memory device

A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.

Cantilever nanoelectromechanical decoder circuit and methods for forming the same

A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.

Memory device having capacitor structure and method of forming the same

A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer. A manufacturing method of a semiconductor structure is also provided.

Method for manufacturing semiconductor structure and semiconductor structure thereof

A physically unclonable function (PUF) device includes first and second inverters, each of which includes a common gate node and a common drain node. The common drain node of the first inverter is electrically connected to the common gate node of the second inverter. The PUF device also includes a common output node, a first resistive memory device (RMD) electrically connected to the common drain node of the first inverter and the common output node, and a second RMD electrically connected to the common drain node of the second inverter and the common output node.

Reconfigurable in-memory physically unclonable function

Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Programming and reading circuit for dynamic random access memory

A memory device, an operation method of a memory cell in a memory device and a semiconductor die are provided. A computational memory cell in the memory device includes: a field effect transistor (FET), with a changeable threshold voltage; and resistive storage devices, connected by a common terminal coupled to a source/drain terminal of the FET. By altering the threshold voltage of the FET, a logic function of the computational memory cell can be changed. During a logic operation, inputs are provided to the computational memory cell as resistance states of the resistive storage devices, and a current passing through a conduction channel of the FET is functioned as an output for the logic operation.

Reconfigurable computational memory device, operation method of the reconfigurable computational memory device and semiconductor die including the reconfigurable computational memory device

A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Three-dimensional integrated structure and manufacturing method thereof

A transistor device including source and drain electrodes, a fin structure extending between and contacting respective sidewalls of the source and drain electrodes, a semiconductor channel layer over the upper surface and side surfaces of the fin structure and including a first and second vertical portions over the side surfaces of the fin structure, and the first and second vertical portions of the semiconductor channel layer both contact the respective sidewalls of the source electrode and the drain electrode, a gate dielectric layer over the semiconductor channel layer, and a gate electrode over the gate dielectric layer. By forming the semiconductor channel layer over a fin structure extending between sidewalls of the source and drain electrodes, a contact area between the semiconductor channel and the source and drain electrodes may be increased, which may provide increased driving current for the transistor device without increasing the device size.

Transistor device having fin-shaped channel and methods for forming the same

A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

Dual gate vertical thin film transistors and methods for forming the same

An active device, a semiconductor device and a semiconductor chip are provided. The active device includes: a channel layer; a top source/drain electrode, disposed at a top side of the channel layer; a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer; a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer; and a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.

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Hsinchu, Taiwan

Yun-Feng Kao