The University of Texas System

Yun Chiu

Benwei Xu

Yanqing Li

Hai Huang

Bo Wu

Jingyi Song

Yuan Zhou

A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.

Pipelined SAR ADC using comparator as a voltage-to-time converter with multi-bit second stage

Disclosed are systems and methods for monitoring biopotential signals in biomedical devices. The disclosure provides a mixed signal background calibration that stabilizes the time-varying coupling gain between the body and an electrode due to motion artifacts. The calibration technique involves a low-level test signal in the form of a one-bit pseudorandom bit-sequence that is injected through a reference electrode to the body, detected by the sensing electrode and recorded along with the bio signals. A digital algorithm is employed in the backend to identify the acquisition channel characteristics while maintaining its normal operation of recording. Programmable gain stages in analog or digital domain(s) can be used to stabilize the overall gain of the channel. The disclosed technique is in the background and not interfering with the normal recording operation(s), and provides continuous monitoring of the ETI and continuous correction of the ensuing channel characteristic degradation due to the ETI variation.

Body-driven pseudorandom signal injection for biomedical acquisition channel calibration

A pipelined SAR ADC includes a first stage and passive residue transfer is used to boost a conversion speed. Owing to the passive residue transfer, the first stage may be released during a residue amplification phase, cutting down a large part of the first-stage timing budget. An asynchronous timing scheme may also be adopted in both the first- and second-stage SAR ADCs to maximize the overall conversion speed. Lastly, a dynamic amplifier with proposed PVT stabilization technique may be employed to further save power consumption and improve the conversion speed simultaneously.

Method and circuit for PVT stabilization of dynamic amplifiers

Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.

Implicit feed-forward compensated op-amp with split pairs

Disclosed are methods and systems implementing digital background calibration techniques for identifying and remedying dynamic path-mismatch errors in time-interleaved analog-to-digital converters (TI-ADC). The disclosed systems and methods employ a calibration technique specifically focuses on removing the timing skew and input bandwidth mismatches by equalizing each sub-ADC in an array to a common reference ADC using direct input derivative information. The errors are identified by correlating the ensuing conversion error to the input derivatives of various orders to identify the mismatch parameters. Simple passive high-pass filters (HPF) are used to extract input derivatives followed by one-bit quantizers.

System and method for dynamic path-mismatch equalization in time-interleaved ADC

Disclosed are systems employing a digital background calibration technique for linearizing the front-end circuits of IF-sampling ADCs. The disclosed systems and methods employ a power series model to eliminate the static non-linearity with split-ADC architecture and LMS algorithm for background learning. The present disclosure utilizes a technique for applying two different offset signals to the input of two conversion paths in the split-ADC architecture. When the system nonlinearity is successfully calibrated, the output difference between the two conversion paths results in a fixed offset that is identical to the offset injected at the input. The disclosed digital background calibration technique can linearize the front-end circuits of high-speed ADCs and significantly reduce power consumption.

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Allen, TX, United States of America

Yun Chiu