Iowa State University Research Foundation Inc

Yuming Zhuang

Degang James Chen

Benjamin Magstadt

The present disclosure relates to a digital-to-analog converter (DAC) linearization system including a DAC, a summing buffer structure, an analog-to-digital converter (ADC), a calculation system, an error look-up table, and an adder. A combination of the DAC, the summing buffer structure, and the ADC sequentially provide first and second ADC output signals, both of which include DAC integral nonlinearity (INL). The calculation system calculates the DAC INL based on the first and second ADC output signals, the error look-up table provides a correction signal mapping to the calculated DAC INL, and the adder provides a calibrated digital input signal to the DAC based on the correction signal. The calibrated digital input signal ensures the DAC to generate an updated output signal with less nonlinearity and improved purity.

Cost effective DAC linearization system

The present disclosure relates to a signal generator with self-calibration including a main digital-to-analog converter (DAC), a calibration DAC, a summing buffer structure, a two-path filter structure, an analog-to-digital converter (ADC), and a control system. The main DAC provides a main DAC output signal with main DAC distortion. The main DAC output signal is calibrated by a calibration DAC output signal to correct at least a portion of the main DAC distortion. The calibration DAC output signal includes information about the main DAC distortion and is generated by a feedback loop including the summing buffer structure, the two-path filter structure, the filter buffer, the ADC, the control system, and the calibration DAC.

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Ames, IA, United States of America

Yuming Zhuang