Matsushita Electric Industrial Co., Ltd.

Yumiko Kataoka

Takashi Koizumi

Noriko Kaku

Naoto Osaka

Hiroyuki Kageyama

Seiichi Moriyama

Hiroyuki Morinaga

When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.

Growing community of inventors

Joyo, Japan

Yumiko Kataoka