Kabushiki Kaisha Toshiba

Yumiko Iyama

Shigeru Atsumi

Junichi Miyamoto

Sumio Tanaka

Nobuaki Ohtsuka

Hironori Banba

Keniti Imamiya

A semiconductor memory device is provided which incorporates a voltage generation circuit capable of generating a high voltage even when a low power voltage is applied to the device. To control the gate voltage of each cell included in a memory cell array, a negative voltage generating circuit connected to a row decoder is included in a boosting circuit. In the case of using a single power of a low voltage, the negative voltage generating circuit generates a negative high voltage during, for example, data erasing. The gate of each P-channel MOS transistor for data transfer is supplied with a pulse signal with an amplitude based on a voltage VCCH which is higher than an external power voltage VCC and obtained by boosting the voltage VCC. As a result, a high voltage can be transferred and output efficiently even if the external power voltage is low.

Semiconductor memory device with high voltage generation circuit

A semiconductor memory device includes a memory cell transistor, a voltage switching circuit supplied with a first voltage for data readout and a second voltage for data write and selectively generating one of the first and second voltages in response to a write control signal, a first driving circuit supplied with an output from the voltage switching circuit and driving the gate of the memory cell transistor in response to a memory cell selection signal, a sense circuit for sensing data of the memory cell transistor by comparing a sense potential corresponding to data from the memory cell transistor with a reference potential, a reference cell transistor for generating the reference potential, and a second driving circuit supplied with the output from the voltage switching circuit and driving the gate of the reference cell transistor in response to the write control signal.

Nonvolatile semiconductor memory device having reference potential

A nonvolatile semiconductor memory according to this invention is so constructed that different data readout references are used in an ordinary readout mode and in a program verification mode. The different read-out references can be set by changing reference input potential VREF supplied to a differential sense amplifier for amplifying a potential derived onto a bit line from a memory cell, or by changing an input threshold level of a circuit for sensing the potential on the bit line. In this case, the readout reference in the program verification mode is set severe, or high, in comparison with that in the ordinary readout mode.

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Yokohama, Japan

Yumiko Iyama