Denso Corporation

Toyota Jidosha Kabushiki Kaisha

Denso Corpora Tion

Yuma Kagata

Nozomu Akagi

Hitoshi Yamaguchi

Masaru Senoo

Tsuyoshi Yamamoto

Akitaka Soeno

Masakiyo Sumitomo

Shinya Iwasaki

Jun Sakakibara

Makoto Kuwahara

Noriyuki Kakimoto

Jun Okawara

Hiroshi Hosokawa

Takashi Kuno

Toshitaka Kanemaru

Satoshi Kuwano

Kenta Hashimoto

Tomoki Akai

Nozomu Akagai

Keita Hayashi

A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

Semiconductor device

An insulated gate bipolar transistor includes: a semiconductor substrate; an emitter electrode arranged on one main surface of the semiconductor substrate; and a trench gate arranged in a rectangular trench having a rectangular shape and disposed on the one main surface of the semiconductor substrate. The semiconductor substrate includes a body contact region and an emitter region in a rectangular region surrounded by the rectangular trench. The rectangular trench has a straight trench that constitutes one side of the rectangular trench. The body contact region is in contact with a side of the straight trench. The emitter region is in contact with the side of the straight trench, and is adjacent to the body contact region. The body contact region has a protrusion portion protruding in a depth direction from a center portion of the body contact region.

Insulated gate bipolar transistor and manufacturing method thereof

A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.

Switching device

A semiconductor device has a deep layer with a higher impurity concentration than that of a super junction structure. The deep layer is formed from a position deeper from a surface of a semiconductor layer by a predetermined depth, and comes in contact with a high impurity layer and also comes in contact with the super junction structure. The deep layer overlaps with a portion between a first end which is an outermost peripheral side of a portion that comes in contact with the high impurity layer in a front surface electrode and an end on an outer peripheral side in the high impurity layer when viewed from a substrate normal direction.

Semiconductor device and method of manufacturing same

The element electrodes of a semiconductor element are disposed in a cell region, while an outermost peripheral electrode electrically connected to a semiconductor substrate is disposed in a peripheral region. In the peripheral region, a second-conductivity-type layer is disposed above a super-junction structure. A potential division region is disposed above the second-conductivity-type layer to electrically connect the element electrodes and the outermost peripheral electrode and also divide the voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages. A part of the potential division region overlaps the peripheral region when viewed from the thickness direction of the semiconductor substrate.

A semiconductor device includes a vertical semiconductor element having a super junction structure constructed of a first conductivity-type drift layer disposed on a surface of a semiconductor substrate and second conductivity-type regions having a stripe shape defining a longitudinal direction in one direction and being arranged at a predetermined column pitch in the drift layer. When a surplus concentration obtained by dividing a difference between an electrical charge of the second conductivity-type region and an electrical charge of a first conductivity-type region by the column pitch is i, a depth of the super junction structure is z, a surplus concentration gradient as a change of the surplus concentration i per unit depth dz is di/dz, and a central withstand voltage in which a margin is added to a desired withstand voltage is V, the super junction structure is configured such that the surplus concentration gradient di/dz satisfies a relation of 

Semiconductor device with vertical semiconductor element

A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.

Semiconductor device and manufacturing method of the same

A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.

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Kariya, Japan

Yuma Kagata