Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Postech Research and Business Development Foundation

Yulhwa Kim

Hyungjun Kim

Jinseok Kim

Jae-Joon Kim

Sungho Kim

Dusik Park

Jaejoon Kim

Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Electronic device for configuring neural network

Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Artificial neural network circuit

A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

Dividing neural networks

A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.

Growing community of inventors

Daegu, South Korea

Yulhwa Kim