Elpida Memory, Inc.

Hitachi, Ltd.

Micron Technology Incorporated

Olympus Corporation

Hoya Corporation

Olympus Imaging Corporation

Other

Mitsubishi Chemical Corporation

Hitachi Ulsi Systems Co., Ltd.

Yuko Watanabe

Shinichi Miyatake

Koichi Shintani

Yoko Saito

Tomoko Kobayashi

Riichiro Takemura

Tomonori Sekiguchi

Satoru Akiyama

Hitoshi Kamura

Kenichi Shinde

Hiroaki Nakaya

Takeshi Mitsuishi

Yukihiro Takahashi

Takefumi Shirako

Isamu Fujii

Hiroki Takei

Akinori Kobayashi

Hiroki Fujisawa

Hiromasa Noda

Seiji Narui

Yoshiro Riho

Koji Arai

Yoji Idei

Toru Tagawa

Homare Sato

Kosuke Goto

Hiroshi Kuzui

Riho Honjo

Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier, a second sense amplifier, a first pair of lines, and a second pair of lines. The first sense amplifier includes a first pull-up sense amplifier and a first pull-down sense amplifier. The first pair of lines electrically connects a first pull-up sense amplifier of the first sense amplifier to a first pull-down sense amplifier of the first sense amplifier. The second pair of lines electrically connects the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of the first pair of lines and three wiring twists of the second pair of lines.

Layouts for sense amplifiers and related apparatuses and systems

Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier including a first pull-up sense amplifier, a first pull-down sense amplifier, and a first pair of lines connecting the first pull-up sense amplifier to the first pull-down sense amplifier. The apparatus also includes a second sense amplifier adjacent to the first sense amplifier. The second sense amplifier includes a second pull-up sense amplifier, a second pull-down sense amplifier, and a second pair of lines connecting the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of at least one of the first pair of lines or the second pair of lines in a region of the first pull-up sense amplifier and the second pull-up sense amplifier.

A controller within a lens drive device, the controller comprising an open loop control section that performs open loop control of the stepping motor using a given excitation position change and a given drive voltage, and a closed loop control section that, at the time of rotating the stepping motor, calculates tracking lag for change in rotational position for change in excitation position, and performs closed loop control of drive speed and drive voltage of the stepping motor in accordance with a control error, which is a difference between target tracking lag and tracking lag, wherein the closed loop control section performs at least open loop control of drive voltage during an acceleration operation of the stepping motor, as well as closed loop control of drive voltage and drive speed in accordance with control error by transitioning to closed loop control of drive voltage when an acceleration operation is completed.

Lens drive device and lens drive method

An imaging apparatus includes an imaging unit for capturing a subject and generating image data of the subject, an operation input unit for receiving inputs of operation signals containing a release signal for instructing the imaging unit to shoot, an acceleration detector for detecting an acceleration of the imaging apparatus, a state detector for separately detecting a case in which the imaging apparatus is overland, a case in which the imaging apparatus is underwater and a photographer shoots while swimming, and a case in which the imaging apparatus is underwater and the photographer shoots while changing a water depth, and a control unit for performing operation control depending on an input into the operation input unit and/or into the acceleration detector according to a state detection result by the state detector.

Imaging apparatus

A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

Semiconductor device having sense amplifier

A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Semiconductor memory device having a sense amplifier circuit with decreased offset

A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer

Bit lines and a pair of two tungsten wires having the same widths are formed at a portion where a through-hole is to be formed such that the bit lines and the tungsten wires are arranged at regular intervals. A through-hole for connection to another wiring layer is formed between the tungsten wires. A connection wiring made of tungsten is formed over the through-hole so as to have a predetermined margin around the through-hole. In a photolithography process, a slit having a small width enough to be insensitive to a photo-resist is formed so as to span the through-hole.

Layout method for miniaturized memory array area

Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Semiconductor memory device

A method for producing an optical element having a multi-layered antireflection film formed on a synthetic resin substrate, in which the antireflection film formed has good heat resistance, and its heat resistance lowers little with time. At least one high-refraction layer of the multi-layered anti-reflection film contains niobium oxide, zirconium oxide, yttrium oxide, and optionally aluminum oxide. High-refraction layers can be formed within a shorter period of time while not detracting from the good physical properties intrinsic to the layers.

Composition for vapor deposition, method for forming an antireflection film, and optical element

A method for producing a composition for vapor deposition comprising sintering a vapor source mixture prepared by mixing vapor sources that contain titanium dioxide and niobium pentoxide. The method is capable of forming a high-refraction layer even in low-temperature vapor deposition on a substrate. An antireflection film is formed having good scratch resistance, good chemical resistance and good heat resistance, of which the heat resistance decreases little with time, that is useful in a variety of optical elements.

Method for producing composition for vapor deposition, composition for vapor deposition, and method for producing optical element with antireflection film

A detergent composition comprising a sucrose fatty acid ester and a salt of long-chain carboxylic acid ester of lactic acid having a purity of at least 80 mol %. The detergent composition is highly safe, is weak acidic or neutral so that it has low irritation to the skin, is excellent in detergent properties such as detergency, foaming power and stability in hard water and also in feeling upon use, and is free from undesired color or odor, so that it is suited particularly as food and dish detergents, and skin and hair detergents such as shampoo, body shampoo, face wash and hand soap.

Detergent composition

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Tokyo, Japan

Yuko Watanabe