Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Yuko Ito

Satoru Isomura

Atsushi Shimizu

Tohru Kobayashi

Takeo Yamada

Keiichi Higeta

Kunihiko Yamaguchi

Kengo Miyazawa

Kazuo Tanaka

Toshio Yamada

Kozaburo Kurita

Mikinori Kawaji

Hideki Sakakibara

Tomoji Nakamura

Koki Tsutsumida

Sukehiro Yoshida

Yoshuhiro Fujimura

Yasuyoshi Sunaga

Atsushi Hazeyama

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S) and a predetermined linearity condition (S).

Semiconductor integrated circuit

A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk. The method calculates the delay by using the total capacitance in consideration of the actual load after the layout and wiring, carries out the layout, wiring and modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the delay by using the total capacitance in consideration of the actual load and crosstalk, carries out the modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the crosstalk noise by using the total capacitance and coupling capacitance in consideration of the actual load, carries out the modification of wiring repeatedly until malfunctioning subsides, and uses data after the final layout and wiring for mask data.

Design method of semiconductor device

The present invention is to provide a method of computing wiring capacitance to be able to get parasitic capacity depending on the wiring at high speed and with great accuracy, and to provide a method of computing signal propagation delay due to cross talk to be able to remove surplus margins at high speed when delay is predicted. In design of LSIs such as microprocessors or the like, total capacity Ctotal per unit length is determined about each of a plurality of models altering adjacent wiring ((a) no adjacent wiring, (b) one-side adjacent wiring, and (c) both-sides adjacent wiring) and/or crossing ratios ((i) 0%, (ii) 33%, (iii) 67%, and (iv) 100%) and, thereby, a library is formed from these to design the LSI. Regarding characteristic of this total capacity per unit length, the capacity depending on increase of the crossing ratio has a high increase rate in an area of a low crossing ratio, while the capacity depending on increase of the crossing ratio has the low increase rate in high crossing ratio. Regarding a case of no adjacent wiring, the capacity depending on increase of crossing ratio has a high increase rate in comparison to a case of one-side or both-sides adjacent wiring.

Method of computing wiring capacitance, method of computing signal propagation delay due to cross talk and computer-readable recording medium storing such computed data

A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.

Semiconductor integrated circuit device and method of manufacturing the

A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.

Semiconductor integrated circuit device with interleaved memory and

A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.

Integrated circuit having alternate rows of logic cells and I/O cells

Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.

Semiconductor device and semiconductor module having auxiliary high

A semiconductor integrated circuit device has a plurality of emitter-coupled logic (ECL) gates. Separate power source wiring lines are provided for current switch circuits and emitter follower output circuits for the gates. The separate sets of power source wiring lines are respectively coupled to the corresponding external terminals of the semiconductor integrated circuit device. The power source wiring lines for each set are arranged adjacent one another on a semiconductor chip in order that they may be short circuited or kept separated depending upon the package structure of the semiconductor integrated circuit device.

Growing community of inventors

Hamura, Japan

Yuko Ito