Hitachi, Ltd.

Yukitoshi Tsuboi

Masuo Oku

Teiji Okamoto

Hiroki Mizosoe

Masaru Takahashi

Shigeru Hirahata

Masaaki Takizawa

Yukio Fujii

Tetsuya Ikeda

Kenji Ichige

Hiromi Watanabe

Hiroshi Gunji

Yoshinobu Igarashi

Hiroyuki Mizosoe

Masahiro Yasuoka

Shuji Shinohara

Takayuki Miyo

In a decoding/displaying device, the memory capacity or mapping to B pictures is set in consideration of a decoding waiting period, thereby avoiding the competition between a write-in operation and a read-out operation for a memory. Therefore, the decoding operation of coded picture data can be performed with no decoding waiting period.

Decoding and displaying device for coded picture data

Decoding/displaying device for decoding/displaying coded picture data

An apparatus for picture decoding includes a decoder unit for obtaining decoded picture data by decoding coded data of a video signal coded by at least one of intra-frame coding (I frame), inter-frame coding (P frame), and frame-interpolation coding (B frame); a memory unit including a first frame memory, a second frame memory, and a third frame memory commonly connected to one data bus and one address bus; a display unit for reading the decoded picture data stored in the memory unit in field units based on a display synchronization signal and obtaining interlace-scanned display picture data; and a time control unit for reading the decoded picture data from the first frame memory and the second frame memory as reference frames for the B frame, and for controlling a time difference between a time of writing decoded picture data in the third frame memory, and a time of reading decoded picture data for display by the display unit, from the third frame memory, for reading decoded picture data before rewriting the same addresses, thereby attaining simultaneous read and write of the third frame memory at frame units.

Apparatus for picture decoding having frame memories commonly connected

In order to increase a coded data buffer size and provide an OSD area within a 16 Mbit memory for picture signals of NTSC and systems, a display data area of the memory is made 2(N+1)/4N times a frame when a picture size is large.

Memory control system and picture decoder using the same

A decoding device is provided including a code FIFO memory unit for sequentially storing a bit stream, a barrel shifter for shifting and then outputting codes properly, an accumulator for computing the shift amount of the barrel shifter and issuing a request to read data to the code FIFO memory unit, a DCT coefficient decoder for decoding DCT coefficients, a variable-length code decoder for decoding variable-length codes other than DCT coefficients, a fixed-length code decoder for decoding fixed-length codes, a register unit for storing decoded data, a decoding controller for controlling the decoders in accordance with the decoded data stored in the register unit and decoded data output by the decoders and a memory controller for controlling operations to store DCT coefficients in a memory unit A. The DCT coefficient decoder, the variable-length code decoder and the fixed-length code decoder are connected in parallel to the output of the barrel shifter and the memory controller is controlled by the decoding controller. By virtue of this structure, the decoding device is capable decoding a bit stream comprising variable-length codes mixed with fixed-length codes. The decoding device is also capable of changing processing of a next code in accordance with decoded codes. Further, these operations can be implemented by means of a simple and reasonable configuration. On top of that, the process of decoding codes at a required high speed is carried out by an independent circuit, allowing the processing power of the decoding circuit to be enhanced.

Decoding device for decoding a variety of code signals

A digital video signal recording and reproducing apparatus and method wherein a basic block is constituted by a plurality of pixels of video signals. A picture data compressing unit effects data compression of the video signals so that a compression data quantity after data compression becomes a constant with respect to a compression block constituted by a plurality of the basic blocks, and the compressed data o the video signals are recorded on a data recording medium. A compression block setting sets a number of the basic blocks to constitute the compression block in response to different operation modes of the digital video signal recording and reproducing apparatus which are different in at least one of resolution of the video signals, recording time and data compression system, and controls the picture data compressing unit so that the number of the compression blocks of the video signals recorded on one track of the data recording medium after data compression by the picture data compressing unit becomes M in a first operation mode, where M is a positive integer, and the number of the compression blocks becomes a positive integer in each of the other operation modes.

Digital video signal recording and reproducing apparatus and method for

A moving picture data recording/reproducing system. In recording operation, moving picture data of a first frame row including frames selected from frames of an input picture signal for every predetermined number of frames are coded in accordance with an intra-frame coding method in which coding is completed within each frame, while picture data of a second frame row including the other frames are coded by an inter-frame coding method assuring a high compression ratio. The coded data resulting from the inter-frame coding and the intra-frame coding are multiplexed by interleaving them in the order of the frame numbers, the multiplexed data being then recorded on a recording medium. In reproducing operation, the multiplexed data are read out for reproducing the moving picture signal or alternatively the intra-frame coded data of the first frame row are selectively read out for reproducing the moving picture signal.

Picture data recording/reproducing system for recording compressed

An image data transfer system constructed of an image data transfer unit, transmission medium and image data reproduction unit. In the image data transfer unit, an input video signal is transformed into image data through sampling and quantization, the image data are coded in a predetermined image coding method, and transferred to the transmission medium. In the image data reproduction unit, the coded data transferred by the transmission medium are decoded in a predetermined image decoding method, the original video signal is restored from the decoded data. A data transfer speed and transfer scheme are selected such that the total coded data amount for the input video signal over a predetermined time duration becomes equal to or smaller than a transferable data amount determined by a data transfer speed from the transmission medium to the image data reproduction unit and by the predetermined time duration. Data transfer information on the selected data transfer speed or information on the transfer scheme is transferred to the transmission medium along with the coded data.

Image data transfer method and apparatus therefor

An entropy coding system in a code assign system for processing image coded data such that for data (particular data) having a particular value, a run length coding is achieved on a run length thereof and for data (nonparticular data) having a value other than the particular value, a Huffman coding is conducted on the value thereof so as to generate a coded or resultant code. When achieving the Huffman coding on the nonparticular date, for the nonparticular data immediately following particular data, the coding operation is executed by use of a Huffman coding table including prefix codes, whereas for the nonparticular data not immediately following particular data, the coding operation is achieved by use of a Huffman coding table including prefix codes.

Entropy-coding system

The video memory control apparatus of the present invention has the first and second counters for repetitiously counting the clock signal at an interval of the display cycle period. The second counter is reset by an external synchronization signal. The first counter is reset by the counter reset signal supplied from the counter reset signal generator circuit. The counter reset signal is used to continue resetting the first counter from when the first counter terminates counting the display cycle period to when the second counter terminates counting the display cycle period. When an external synchronization with a phase shift is inputted, the first counter is kept reset by the counter reset signal for a period corresponding to the phase shift of the external synchronization signal. Consequently, in a case of the superimpose display, even if the external synchronization signal undergoes a phase shift, the synchronization can be established again in a short period of time.

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Yokohama, Japan

Yukitoshi Tsuboi