Renesas Electronics Corporation

Yukitoshi Tsuboi

Hideo Nagano

Yutaka Igaku

Masataka Minami

Kenichi Shimada

Masanori Ikeda

Hiroyuki Hamasaki

Naotaka Kubota

Hiroshi Nagaoka

Tadashi Kameyama

Ryosuke Okuda

Takuya Hirade

Yusuke Matsunaga

Yasuhiro Yamakoshi

The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.

Abnormal power supply voltage detection device and method for detecting abnormal power supply voltage

A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Semiconductor device and memory access control method

The subject is to improve the detection performance in the error detection of data using an ECC. A data processing deviceincludes an encoder devicethat includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unitto generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unitgenerates the first ECC for the first data. The encoder unitgenerates the second ECC for the second data obtained by permutating a bit of the first data.

Data processing device and data processing method

A control systemaccording to the present invention is mounted on a moving object. The control systemincludes: an observing devicewhich transmits observation result data indicating an observation result of surroundings of the moving object; a first control instruction devicewhich transmits first control data indicating the control contents determined based on the observation result data; a movement control devicewhich controls movement of the moving object; and a relay devicewhich relays the first control data transmitted from the first control instruction device, to the movement control device. When a second control instruction devicewhich transmits second control data indicating the control contents determined based on the observation result data is provided to the control system, the relay devicetransmits the second control data instead of the first control data, to the movement control device

Control system, relay device and control method

A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Semiconductor device, diagnostic test, and diagnostic test circuit

The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.

Data processing apparatus

To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abnormal interrupt request processing

A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.

Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor deviceaccording to the present invention includes a plurality of CPU corestoeach including a scan chain, and a diagnostic test circuitthat performs a scan test for the plurality of CPU corestoby using the scan chain of the CPU core. The diagnostic test circuitperforms a scan test for each of the plurality of CPU corestoin a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

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Tokyo, Japan

Yukitoshi Tsuboi