Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Hitachi, Ltd.

Nec Corporation

Other

Yukitoshi Hirose

Yutaka Uematsu

Yoji Nishio

Mitsuaki Katagiri

Hideki Osaka

Takashi Suga

Yushi Inoue

Satoshi Nakamura

Satoshi Isa

Shiro Harashima

Takuya Moriya

Chihoko Yokobe

Tatsuya Saito

Seiji Funaba

Hiroya Shimizu

Satoshi Muraoka

Satoshi Itaya

Ken Iwakura

Miho Nomoto

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Semiconductor device

A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip.

A device includes: a wiring board having first and second surfaces opposing each other; and a plurality of memory packages on the first surface. The wiring board includes: a first set of terminals on the first surface; a plurality of second sets of terminals on the first surface; and a plurality of first signal lines. The terminals of the first set receive respective ones of a plurality of first signals supplied from a control device. Each of the second sets is provided for a corresponding one of the memory packages. The terminals of each of the second sets contact the corresponding one of the memory packages. The first signal lines extend from respective ones of the terminals of the first set while coupling respective ones of the terminals of each of the second sets. The first signal lines extend on the first surface without extending in the wiring board.

An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Test method and interposer used therefor

In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.

A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.

Semiconductor device and information processing system

The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips includes a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device also includes a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.

Multilayer semiconductor device

Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the 'm' number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the 'm' number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.

Multichip package or system-in package

A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected. In addition, also on a pull-down side of the driver, a plurality of N-channel transistors to which resistance elements are inserted in series are prepared such that an ON resistance value on the N-channel transistor side and a resistance value of the resistance element can be selected. A driver section having a linear current-voltage characteristic is realized by combination of those described.

Semiconductor device and driver control method

A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package

A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

Method for designing device, system for aiding to design device, and computer program product therefor

A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.

Semiconductor device having a multi-layered semiconductor substrate

The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.

In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

Growing community of inventors

Tokyo, Japan

Yukitoshi Hirose