Kabushiki Kaisha Toshiba

Yukitaka Yoshida

Hiroshi Nakatani

Atsushi Takahashi

Motohiko Okabe

Yoshito Sameda

Jun Takehara

Naoya Ohnishi

Yuuichi Sato

Mamoru Kato

Yoshiyuki Nitta

Hidemitsu Hohki

Naruhiko Aramaki

Yuji Ichioka

Toshikazu Kawamura

Kenji Shigihara

Takashi Omagari

Yoshihiro Asakura

Shunya Maruchi

Hiroshi Nagahisa

In one embodiment, a multiplex control device includes three or more control modules to execute same operations for same input signals, and a majority decision module to output an output signal that matches majority of output signals outputted by the control modules. Each control module includes an input module to convert an input signal into an input value, a first determination module to obtain input values from input modules of respective control modules to determine whether majority of input values among the obtained input values match, an operation executing module to execute an operation using the matched input value to generate an output value, a second determination module to obtain output values from operation executing modules of respective control modules to determine whether majority of output values among the obtained output values match, and an output module to convert the matched output value to generate an output signal.

Multiplex control device

According to an embodiment, a control system has: a logic module substrate that has a logic FPGA on which logic is mounted, a transmission module that transmits an output logic state signal, which is logic state signal representing an interim logic state of a process by the logic FPGA of deriving a logic output signal from the logic input signals, and a logic monitoring device that displays to monitor the logic state signal transmitted from the transmission module. The logic module substrate includes an event detection unit that detects a change in the logic state signal. Only when a change in the logic state signals is detected by the event detection unit, the logic output state signal being transmitted to the transmission module.

Control system, logic module substrate, and logic FPGA

A control device includes: memory diagnosis means for setting a power-on status when an electric power is turned on and diagnosing an ECC memory; restarting means for restarting the control device when the memory diagnosis means detects a correctable error of the ECC memory during the power-on status of the ECC memory; and operation processing means for resetting the power-on status and performing a normal operation when the memory diagnosis means does not detect a correctable error of the ECC memory, while performing the normal operation when a correctable error of the ECC memory is detected because of the restart of the control device by soft reset after the reset of the power-on status but when the control device is not in the power-on status.

Control device

A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line

Growing community of inventors

Fuchu, Japan

Yukitaka Yoshida