Fujitsu Corporation

Yukisato Miyazaki

Teruhiko Saitou

Kazuya Taniguchi

Kouji Okada

Shinji Miyata

Masao Iijima

Kunihiro Ohara

Masayuki Takeshige

Hiroshi Naritomi

Hayato Isobe

Sumitaka Hibino

Teruyoshi Kondo

A clock generation circuit and a clock generation method are provided, which are spread spectrum clock generation and accurate phase control of a reference clock signal and an output clock signal. An input divider unitdivides an input clock signal CLKR by 50 to output a divided input clock signal CLKS. A DLL circuitoperates to obtain delay control signals DCS, DCS. A modulation circuitmodulates, in response to the delay control signals DCS, DCSand a modulation signal MOD output from a modulation control circuit, the divided input clock signal CLKS to output a modulation clock signal CLKN. A phase comparatordetects the phase difference between the modulation clock signal CLKN and a divided inner clock signal CLKM. A clock generation unitgenerates an output clock signal CLKO having frequency corresponding to a phase difference signal from the phase comparator

Clock generation circuit and clock generation method

A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

Spread spectrum clock generation circuit, jitter generation circuit and semiconductor device

A microcontroller, connected to a memory which stores instructions and data, includes an instruction execution unit for reading instructions and data from the memory and processing the read instructions and a prefetch circuit unit that receives the instructions and data read from the memory and detects pseudo instructions included in the instructions and data. A pseudo instruction precedes a branch instruction and indicates the existence of the branch instruction and the branch to address. The prefetch circuit unit includes a prefetch buffer connected between the instruction execution unit and the memory for temporarily storing instructions and data being transferred from the memory to the instruction execution unit and a pseudo instruction buffer for temporarily storing instructions and data located at the address of the branch instruction which follows the pseudo instruction. Then, if the branch is taken, the branch to instructions have been prefetched and are immediately available to the instruction execution unit by way of the pseudo instruction buffer.

Microcontroller having prefetch function

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Method and apparatus for compactly storing instruction codes

Growing community of inventors

Kasugai, Japan

Yukisato Miyazaki