Tdk Corporation

Yukio Terasaki

Naoki Mukaida

Kenzo Kita

Hiroshi Karibe

Tomoyuki Sasaki

Tatsuo Shibata

Yuji Kakinuma

Shogo Yamada

Takeshi Kamono

Tsuyoshi Oyaizu

An arithmetic operation circuit including: a variable resistance element that includes three terminals that are a first terminal, a second terminal, and a third terminal and is configured to be able to change a resistance value; a first electrode connected to the first terminal; a second electrode; a third electrode; a first switching element connected between the second electrode and the second terminal; a second switching element connected between the third electrode and the third terminal; and a capacitor connected between a transmission line connecting the second terminal and the first switching element and the ground.

Arithmetic operation circuit and neuromorphic device

A controller is a controller of an array including a neuromorphic element that multiplies a weight based on a value of a variable characteristic by a signal, and includes a control unit that controls the characteristic of the neuromorphic element by using a discretization step size obtained so that a predetermined condition for reducing an error or a predetermined condition for improving accuracy is satisfied on the basis of a case where a true value of the weight obtained with a higher accuracy than a resolution of the characteristic of the neuromorphic element is used and a case where a discretization step size which is set for the characteristic of the neuromorphic element is used.

Controller of array including neuromorphic element, method of arithmetically operating discretization step size, and program

A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.

Neural network device, signal generation method, and program

A sum-of-products operator including: a first circuit configured to generate a plurality of signals, each of which corresponds to each of a plurality of data; a second circuit including a first operation circuit configured to multiply each of the signals generated by the first circuit by a weight using a plurality of variable resistive elements having variable resistance values, and to calculate a sum of a plurality of results of multiplications; a third circuit configured to calculate a result of summing values corresponding to the data or a result of the summing value after being adjusted; and a fourth circuit including a differential circuit configured to output a difference between a calculated result in the first operation circuit of the second circuit and a calculated result in the third circuit.

Sum-of-products operator, sum-of-products operation method, logical operation device, and neuromorphic device

A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a width of said position of the first part of the magnetic recording layer.

Magnetic domain wall displacement type magnetic recording element and magnetic recording array

The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data.

Memory controller, flash memory system with memory controller, and method of controlling flash memory

First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.

A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.

Memory controller, flash memory system having memory controller and method for controlling flash memory device

A controller included in a flash memory system, which can be applied to a memory interface of a host computer is disclosed. A buffer is used for data exchange operation between the host computer and the controller, and data exchange operation between a flash memory and the controller. A host interface control block as a first control block controls data exchange operation between the buffer and the host computer. A flash sequencer block as a second control block controls data exchange operation between the buffer and the flash memory. The host interface control block controls input and output operation of the buffer, based on a memory control signal and a memory address signal supplied from the host computer. The flash sequencer block controls input and output operation of the buffer at a one-page size of the flash memory.

Flash memory controller, memory control circuit, flash memory system, and method for controlling data exchange between host computer and flash memory

An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.

A memory controller which performs a verification of the state of the erased block is performed prior to the writing operation is disclosed. The memory controller according to said present invention further performs a test operation to judge whether the erased block is a defective block to be disposed or not if the erased block is concluded to be not prefer to store data during the verification. In the case where the block is concluded to be a defective block with a permanent error by the test operation, the block is inhibited to use. In the case where the block is concluded to be a defective block with a transient error by the test operation, on the other hand, the block is treated as new erased block.

Memory controller for flash memory system and method for writing data to flash memory device

The present invention relates to a PC card detachably installed and used for an information processing device such as a personal computer, digital-still-camera and so on to process a variety of information and its objects is to provide a PC card connectable to a plurality of information processing devices without losing the advantages of easy detachability, flexibility and portability originally owned by the PC card. A structure is formed to provide a first interface section,to execute data transfer between a function block supplying a predetermined function for information processing device and a portable PC (omitted in FIG.,), and a second interface section,having a different interface specification from the first interface section to transfer data between the function block,and a desktop PC

PC card

A flash memories (20, 21) are coupled with a host computer (1) through a flash memory controller (2) which has a pair of data buses (27, 28), and a pair of buffer memories (22, 23). Each of said data buses is coupled with a related flash memory, and a related buffer memory, which is coupled with said host computer. Said data buses (22, 23) are controlled to operate simultaneously so that said flash memories are accessed simultaneously in parallel form. A data in said host computer is transferred to said flash memories through said buffer memories and said data buses, and vice versa. All the elements (20, 21, 2) are mounted on a plastics card (100) called a flash memory card, which is coupled with a host computer through a connector. Because of use of a plurality of buses operating in parallel form, the transfer time of data between a host computer and a flash memory card is shortened.

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Tokyo, Japan

Yukio Terasaki