Nippon Electric Co., Ltd.

Kokusai Denshin Denwa Co., Ltd.

Yukio Takimoto

Ryokichi Saga

Toshinori Hotta

Yutaka Yasuda

Keiichiro Koga

A switching matrix enables the impedance to be easily matched at the connecting points of the distributing, the switching and the combining circuits, and of the external circuits. The switching circuit used by the switch matrix, includes PIN diodes, Schottky barrier diodes, field-effect-transistors (FETS), coaxial relays, or mixers. These devices can gain the ON/OFF ratio required for the switching circuit. However, in an M.times.N switch matrix, the input impedance of the switch circuit is usually dependent on the number of inputs or outputs to be selected, and therefore, there are deviations in the ON/OFF ratio required for the switch operations and a resulting deterioration in the signal-to-noise ratio. The present invention provides a switch matrix which is flexible enough to allow easy changes of the number of input/output terminals, with only a small insertion loss, even with a great number of input/output terminals. The switch matrix has a greater ON/OFF ratio, by cascade-connecting the switch circuits in multiple stages, with a smaller output level of deviation which is caused by the routing differences for signals. The switch matrix has a high switching speed, small size, light weight, and low power consumption.

Switch matrix apparatus for satellite-switched TDMA system or the like

On carrying out communication among a plurality of earth stations by the use of a satellite, super-frame time slots are specified on board the satellite at a super-frame period equal to a frame period multiplied by a predetermined natural number in order to synchronize the satellite and the earth stations with the super-frame time slots. The satellite informs each earth station of the super-frame time slots by generating super-frame bursts specifying the super-frame time slots. Alternatively, each earth station generates super-frame bursts to enter the super-frame time slots on the satellite. The satellite informs such earth station of the super-frame time slots by preventing the super-frame bursts from being returned to each station. At any rate, the satellite and each station change one on-line sequence of operation to the other in synchronism with a specified one of the super-frame time slots without any interruption of communication.

Satellite communication system for switching formats with reference to

The invention converts between a cyclic and a general code sequence, each sequence having a succession of normal code blocks and an additional or shorter code block. A zero bit series is hypothetically assumed before the additional code block. In an encoder for producing a cyclic code sequence, the zero bit series is placed before the additional code block by cooperation of a timing control circuit and a divider. In a decoder, a counter times an additional cyclic code block and starts counting while another counter is still counting to time a period, which is the period next preceding a normal cyclic code block, whereby the zero bit series is assumed.

Method and device for conversion between a cyclic and a general code

A group frame synchronization system establishes the frame synchronization to a plurality of time-division multiplexed digital signals by the use of a common synchronization code pattern. The common synchronization code pattern and mutually time-shifted codes of identical pattern are respectively inserted at the transmitting end into vacant time slots of the respective digital signals. At the receiving end, the group frame synchronization signals are extracted and fed to an exclusive OR circuit whose output signal is applied to the group frame synchronization circuit.

Growing community of inventors

Tokyo, Japan

Yukio Takimoto