Fujitsu Corporation

Hitachi, Ltd.

Yukio Otobe

Masahiro Yoshida

Masaya Tajima

Katsuhiro Ishida

Nobuaki Otaka

Toshio Ueda

Kiyotaka Ogawa

Kiyoshi Kohiyama

Hidenaga Takahashi

Kimihiko Kazui

Hideki Miyasaka

Katsuki Miyawaki

Koji Yoshitomi

Shozo Kobatake

Yasunori Ueno

Kouji Maruyama

A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SFthrough SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance levelto a luminance level N.

Display driving method and apparatus

A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SFthrough SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.

A memory control part cyclically assigns time slots to buffer memory parts to respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM . A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of &lsqb;(the number of pixels on one horizontal scanning line)/256&rsqb; in number are generated in an imaginary one horizontal scanning period, where &lsqb; &rsqb; denotes an integer portion of the number in the parentheses. For a buffer memory whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

Method and device for decoding moving picture

A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of subfields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF throuh SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N&plus;1 gradation levels from a luminance level to a luminance level N.

A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N&plus;1 gradation levels from a luminance level 0 to a luminance level N.

A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.

An image processing device has an error distribution unit, and a multiplier. The error distribution unit carries out an error distribution operation to artificially increase the number of shades to be displayed on a display. The multiplier multiplies an input signal by a multiplication coefficient, so that the input signal is separated into display data and error data along a bit boundary and the error distribution operation is carried out on the input signal. Further, a semiconductor integrated circuit has a dither pattern generator, an adder, and an error distribution unit. The dither pattern generator stores a plurality of dither patterns in advance and receives an input image signal, the adder receives the input image signal and a pattern signal from the dither pattern generator, and the error distribution unit carries out an error distribution operation on the output of the adder. Therefore, the image processing device can realize a smooth display characteristic for the entire range of input shades.

Image processor using both dither and error diffusion to produce

Control operations to access a memory changes respective priorities of the operations depending on the situation of the memory, and the operations are arbitrated and scheduled according to the respective, changed priorities, in order to avoid concentration on or rejection of a specific memory access operations and to eliminate an ineffective period. This realizes an efficient memory system without increasing the capacity of a buffer memory, the width of a memory bus, or an operating frequency.

Method controlling memory access operations by changing respective

A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read address upon the first-in first-out memory device. The write address is cleared by a write reset signal, and the read address is cleared by a read reset signal. A delay circuit is provided to coincide an effective timing of the write reset signal in the memory cell array with that of the read reset signal in the memory cell array.

One-chip first-in first-out memory device having matched write and read

A composite video signal generation method and device comprises circuits for processing a digital signal, by which the circuits can be integrated. The method comprises the steps of calculating a digital luminance signal and two digital chrominance signals combined from digital primary color component signals, balance-modulating a subcarrier by the two digital chrominance signals, and combining the balance-modulated signals and the luminance signal. In the balance-modulation step, a series of phase information values by adding one by one a value of a sampling period of the digital primary color component signal per a subcarrier period is obtained, cosine function values and sine function values are operated in response to the phase information values, and the cosine function values and the sine function values are multiplied by the two digital chrominance signals, respectively. Accordingly, phase information values of the device can be varied, and if the sampling period of the system changes, the digital primary color component signals can be converted to the NTSC signal.

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Kawasaki, Japan

Yukio Otobe