Nippon Telegraph and Telephone Corporation

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Nec Corporation

Nec Electronics Corporation

Nippon Telephone and Telegraph Corporation

Yukio Okazaki

Satoshi Shigematsu

Hiroki Morimura

Katsuyuki Machida

Takahiro Hatano

Mamoru Nakanishi

Akinori Daimo

Toshio Kobayashi

Hakaru Kyuragi

Toshishige Shimamura

Koji Fujii

Namiko Ikeda

Takashi Morimoto

Hiroshi Inokawa

Masayasu Miyake

Kenichi Saito

Shigeki Nakamura

Tadashi Morita

Hirofumi Nishimura

Kenji Miyanaga

Masakatsu Maeda

Asako Hamada

Hiroki Suto

Hisaya Ishihara

Chikara Yamaguchi

An object detection device includes: a classifier that receives, from a radar device that transmits a transmission wave and receives a reflected wave that is the transmission wave reflected by an object around a subject vehicle, detection result information indicative of an intensity, an azimuth, and a Doppler velocity obtained from a Doppler frequency shift of the reflected wave, and determines whether the detection result information is first detection result information corresponding to a moving object or second detection result information corresponding to a still object; a calculator that calculates distances from the radar device to reflection points of the moving object on the basis of the first detection result information; and an output that supplies, to a predetermined device, first reflection point information indicating the distances of the reflection points and azimuths of the reflection points based on the radar device.

Object detection device and recording medium

Provided is a phased array transmission device including: a plurality of transmission branches, each being provided with a phase shift unit that applies a phase rotation to a baseband signal, a DC offset correction unit that adds a first correction value to an output signal of the phase shift unit, and a mixer that subjects an output signal of the DC offset correction unit to a frequency conversion to a high frequency band; and a correction control unit that calculates a second correction value with which a carrier leak component included in an output signal of the mixer is minimized, for each of a plurality of candidates for a phase rotation amount that is set for the phase rotation, and determines the first correction value on the basis of the second correction value.

Phased array transmission device and carrier leak correction method

A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.

Bias circuit for use with amplifier circuit, control method thereof, and signal amplifier

A wireless communication apparatus includes multiple antenna devices, a signal generator, a phase shifter, a phase controller, and a quadrature error corrector (phase error corrector and amplitude error corrector). The signal generating circuitry, in operation, generates an IQ signal having an I signal and a Q signal. The plurality of phase shifting circuitry provided for each of the plurality of antenna devices, in operation, generates a plurality of combination signals by combining the I signal and the Q signal based on a predetermined combining scheme. The phase controlling circuitry, in operation, controls the predetermined combining scheme in each of the plurality of phase shifting circuitry. The quadrature error correcting circuitry, in operation, corrects at least one of amplitude combining scheme and phase combining scheme of the predetermined combining scheme in a correction of the predetermined combining scheme.

Wireless communication apparatus and method

A power amplifier includes an output terminal, capacitive element groups including capacitive elements, and amplifier groups including amplifiers. Capacitive elements of the capacitive element groups are disposed on a first circle whose center is located on the output terminal. Amplifiers of the amplifier groups corresponding to the capacitive elements of the capacitive element groups are disposed on a second circle, which is concentric with and larger than the first circle. Each of the capacitive elements of the capacitive element groups is connected to both the output terminal and the corresponding amplifier of the amplifiers of the amplifier groups.

Power amplifier and transmission device

An SCPA includes a pad, capacitative elements, amplifiers on an IC chip. The capacitative elements are disposed on a first circle whose center is located on the pad. The amplifiers which correspond to the capacitative elements are disposed on a second circle which is a concentric circle larger than the first circle. The pad, each of the capacitative elements, and a corresponding one of the amplifiers are aligned in a line so that the length of wiring is the shortest.

This invention includes an image quality priority level decision processing unit () which evaluates the magnitude of an image quality of each of a plurality of first image data formed from biometric images associated with the same target on the basis of a specific index having the relationship of a monotone function with authentication accuracy of biometric authentication, and outputs each of the first image data upon adding a priority level thereto on the basis of the evaluation result, a first image storage () unit which stores each of the first image data having a priority level added thereto from the image quality priority level decision processing unit (), a second image storage unit () which stores second image data used for comparison/collation with the first image data, an image collation unit () which compares/collates the second image data stored in the second image storage unit () with the first image data stored in the first image storage unit () and outputs the comparison/collation result, and a control unit () which controls each of the units. The control unit () causes the image collation unit () to compare/collate the second image data stored in the second image storage unit () with the first image data stored in the first image storage unit () in accordance with the priority levels, and outputs the comparison/collation result from the image collation unit ().

Biometric image collation apparatus and collation method therefor

A sensor cell includes a sensor electrode () formed on a substrate (), a signal output unit () which outputs a signal corresponding to a capacitance (Cf) formed between the sensor electrode and the surface of a finger (), a high-sensitivity electrode () formed on the substrate so as to be insulated and isolated from the sensor electrode, and a potential controller () which controls the potential of the finger surface via a capacitance (Cc) formed between the high-sensitivity electrode and the finger surface by controlling the potential of the high-sensitivity electrode. In this arrangement, when the resistance of the finger is high, the potential of the finger surface can be controlled so as not to fluctuate with the potential change of the sensor electrode. This makes it possible to increase the sensitivity of detection of the capacitance formed between the sensor electrode and the finger surface, so ridges and valleys of the finger surface can be clearly discriminated by outputs from a plurality of sensor cells.

Surface shape recognizing sensor device

A master latch () is formed from a static circuit, and a slave latch () is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.

Master-slave flip-flop, trigger flip-flop and counter

An image processing apparatus includes an image correcting section. When an image of an object is input, the image correcting section performs correction processing for the input image including the object image and outputs the corrected image as an image required for authentication of the object. An image processing method is also disclosed.

Image processing method and apparatus

A first control potential setting means () generates a first control potential (N) which reverses the magnitude relationship with a second control potential (N) when an input signal (IN) reaches the vicinity of a logical threshold value. A second control potential setting means () generates the second control potential (N) which changes in the same direction as the input signal (IN), in accordance with a change in input signal (IN). An output means () includes transistors (Q, Q), and generates an output signal (OUT) having a predetermined potential on the basis of the first control potential (N), the second control potential (N), and a reset signal (RSET). A reset means () turns off the transistor (Q) while a waveform shaping circuit is in operation.

Waveform shaping circuit

An image capturing apparatus includes an image capturing section and capture control section. The image capturing section converts the shape of an object into an electrical quantity in accordance with the parameter value set in a parameter setting section, and outputs image data representing an image corresponding to the shape of the object. The capture control section receives the image data output from the image capturing section, calculates an evaluation index for evaluating the image quality of the image from the image data. If the evaluation index falls outside the range of a preset reference value, the capture control section changes the parameter value set in the parameter setting section so as to make the evaluation index fall within the range of the reference value to output the image data which is received from the image capturing section and the evaluation index of which falls within the range of the reference value. An image capturing method and a fingerprint collation method and apparatus are also disclosed.

Image capturing method and apparatus and fingerprint collation method and apparatus

There is disclosed a phase shifter using a polyphase filter, which achieves a broad band, suppresses errors in both amplitude and phase, and achieves low power consumption. A driving section includes a voltage-to-current conversion circuit for converting a voltage value of an input signal Si into a current value, and outputting an input current signal Ci. An RC polyphase filter outputs a corresponding polyphase phase-shifted current signal Co according to supplying of the input current signal Ci. A load circuit includes a polyphase current-to-voltage conversion circuit for converting a current value of the polyphase phase-shifted current signal Co into a voltage value, and outputting an output signal Vo.

Phase shifter with an RC polyphase filter

In a gain variable amplifier apparatus, a thermal voltage proportional circuit converts a first control voltage into a second control voltage proportional to a thermal voltage, the gain of a gain variable amplifier being controlled by the second control voltage.

Gain variable amplifier apparatus having improved gain control linearity characteristics

A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.

Growing community of inventors

Kanagawa, Japan

Yukio Okazaki