Fujitsu Corporation

Yukio Nishimura

Kazunori Masuyama

Sudheer Miryala

Satoru Nishita

Patrick N Conway

Jeremy J Farrell

Hitoshi Oi

Prabhunandan B Narasimharmurthy

Prabhu Murthy

Prabhunandan B Narasimhamurthy

A first controller stores externally input data to a memory of the first controller, reads data stored in the memory of the first controller and transmits the data to a second controller through a first controller bridge, detects a failure at the first controller bridge in transmission of the data. The second controller receives the data through a second controller bridge, writes the received data into a memory of the second controller, and determines whether the failure is caused by the first controller if a failure occurs in the memory controller and the second controller bridge. If a failure is detected in the first controller and the second controller and the failure is caused by the first controller, the first controller transmits the data causing the failure during transmission through the first controller bridge and the second controller receives the data through the second controller bridge.

Storage apparatus and control method for storage apparatus

A multi-core processor which includes a plurality of processor dies. The multi-core processor has a first processor core which processes a first task and a second processor core which processes a second task. The first processor core and the second processor core are formed on each of the plurality of processor dies. When the first processor core makes a request for the second task processing in processing the first task, information on the second task is stored in a memory area used by the first processor core and interrupt notification is made to each of the second processor cores provided respectively on the plurality of processor dies. Each of the second processor cores having received the interrupt notification accesses the memory area used by the first processor core provided on the same processor die as the processor die on which the second processor core is provided.

Multi-core processor, control method thereof, and information processing apparatus

A method and system enables dynamic support of memory mapping devices in a multi-node computer system. One of central process unit (CPU) nodes determines a total amount of MMIO address spaces that are needed for all MMIO devices and generates an optimized granularity to support the total amount of MMIO address spaces. Based on the granularity, a CPU node controller configures MMIO range registers of the interconnect and other MMIO registers in IO nodes and CPU node controllers to support dynamic changes of MMIO address space requirements of the system.

Dynamic determination of memory mapped input output range granularity for multi-node computer system

A method and system transfers data between intra-node firmware and inter-nodes firmware in a multi-node computer system using reduced hardware resources. A set of control codes and data transfer functions are provided to enable data communications between computer nodes and inter-nodes controller through a one-byte control module and a one-byte data module.

Data transfer in multi-node computer system

A domain partitioning system for a multi-node computer system is disclosed. An external server manager is coupled to a domain configuration unit by a dedicated sideband channel. The server manager has write privileges to the domain configuration unit that allows the server manager to control the domain partitioning and the routing tables. None of the domains of the computer system are permitted write access to the domain configuration unit. In one embodiment, the domain configuration unit is a set of domain partition registers and routing table registers coupled to a system interconnect.

Growing community of inventors

Ishikawa-ken, Japan

Yukio Nishimura