Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Yukio Nishida

Tomohiro Yamashita

Hidekazu Oda

Hirokazu Sayama

Toshiyuki Oishi

Yuki Yamamoto

Shuichi Ueno

Kazunobu Ohta

Satoshi Shimizu

Yoshiki Yamamoto

Katsuyuki Horita

Hirofumi Shinohara

Jiro Yugami

Hiroshi Umeda

Shigeru Shiratake

Katsumi Eikyu

Masayoshi Shirahata

Takashi Terauchi

Masashi Kitazawa

Akinori Kinugasa

Kenichi Ohto

To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left. Next, a silicon film is formed over the semiconductor substrate, then the silicon film is patterned in the memory cell region, and, in the peripheral circuit region, the silicon film is left so that an outer peripheral portion of the remaining metal film is covered with the silicon film. Subsequently, in the peripheral circuit region, the silicon film, the metal film, and the insulating film are patterned for forming an insulating film portion formed of the insulating film, a metal film portion formed of the metal film, and a conductive film portion formed of the silicon film.

Memory semiconductor device with peripheral circuit multi-layer conductive film gate electrode and method of manufacture

The present invention improves the performance of an image sensor. In a planar view, fluorine is introduced into a part overlapping with a channel region in a gate electrode GEof an amplification transistor and is not introduced into the interior of a semiconductor substrateS. Concretely as shown in FIG., a resist film FRis patterned in the manner of opening the part planarly overlapping with the channel region in the gate electrode GE. Then fluorine is injected into the interior of the gate electrode GEexposed from an opening OPby an ion implantation method using the resist film FRin which the opening OPis formed as a mask.

Solid-state image sensing device and method for manufacturing the same

Patterning a conductive film in a manufacturing method of semiconductor device

MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment. The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.

Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device

The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part.

Semiconductor device including image pick up device

Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.

Semiconductor device and manufacturing method thereof

A gate structure (), an LDD region () and a sidewall () are provided in this order. Arsenic ions () are thereafter implanted into the upper surface of a silicon substrate () by tilted implantation. The next step is annealing for forming an MDD region () in the upper surface of the silicon substrate (). The MDD region () and the gate structure () do not overlap one another in plan view. Further, the MDD region () formed into a depth shallower than that of the LDD region () is higher in concentration than the LDD region (). Thereafter a source/drain region () higher in concentration than the MDD region () is provided by vertical implantation into a depth greater than that of the LDD region ().

Method of manufacturing semiconductor device

A gate insulating film, two polysilicon filmsand, and a silicon nitride filmare successively laminated on a semiconductor substratein this order. Each of the polysilicon filmsandcontains phosphorus. The polysilicon filmhas a region having a phosphorus concentration higher than that of the polysilicon film. Gate electrodes, andare formed on the gate insulating filmby partly etching the polysilicon filmsandand the silicon nitride film. In this case, the etching rate of the region of the polysilicon film, having a phosphorus concentration higher than that of the polysilicon film, is higher than that of the polysilicon film. Due to this difference, notches are formed at the bottom portions on side surfaces of respective gate electrodes, and

Manufacturing method for a semiconductor device

A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

MOSFET with graded gate oxide layer

CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor ( B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).

A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effect transistor includes a gate electrode, source and drain regions, and a channel region. The channel region includes a pair of lightly doped impurity regions having a relatively low impurity concentration as well as a heavily doped impurity region located between the lightly doped impurity regions and having a relatively high impurity concentration.

Semiconductor device

Arsenic is ion-implanted through a thin insulative through film formed on an active region in the vicinity of a gate insulating film towards the inside of a semiconductor substrate at a dose of 3E13 cm at an energy of 100 keV at a tilt angle, which is made by an ion implantation direction and a normal direction (NL), of 45 degrees with respect to a (100) surface of the semiconductor substrate, with which a channeling phenomenon can be caused. Next, phosphorus is ion-implanted towards the inside of the semiconductor substrate at a dose of 1E13 cm at an energy of 50 keV at an angle with which no channeling phenomenon can be caused. After that, a sidewall is formed and then arsenic is ion-implanted towards the inside of the semiconductor substrate at a dose of 4E15 cm at an energy of 50 keV at an angle with which no channeling phenomenon can be caused, to form n layers.

Semiconductor device with lightly doped drain layer

An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film or an end portion of the field oxide film is eroded, therefore, the metal silicide layer is not directly connected to a well, a channel cut injection layer or a channel injection layer and the distance between a pn junction formed by the source/drain and the well and an end portion of the metal silicide layer is not reduced, whereby reliability of an element operation is improved such that a leakage current is suppressed while maintaining the depth of the source/drain. Thus obtained are a semiconductor device and a method of fabricating the same which can attain a high-speed operation without increasing the depth of the source/drain while maintaining a sufficient contact width and can reduce a junction leakage current with no deterioration of the element characteristics following refinement.

There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate ( ), an element isolation insulation film ( ), a gate structure selectively formed on the main surface of the silicon substrate ( ), and a sidewall ( ) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film ( ) formed of a silicon oxide film, a gate electrode ( ) formed of polysilicon, and a cobalt silicide layer ( ) stacked in this order. The semiconductor device further comprises a source/drain region ( ) selectively formed in the main surface of the silicon substrate ( ) and a cobalt silicide layer ( ) formed in the main surface of the silicon substrate ( ), extending to a point under an end portion of the gate structure from a portion of the source/drain region ( ) exposed from the sidewall and the gate structure.

Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches ( ) of different widths are formed on a semiconductor substrate ( ) on which an underlying film ( ) such as a silicon oxide film and a mask material ( ) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench ( ) is filled up. At this time, the wider trench ( ) has an unfilled space in its central portion. a The surface of the substrate ( ) is then vertically etched back until it is exposed in the trench . With insulating films ( ) in the trenches ( ) as a mask, the surface of the substrate ( ) is anisotropically etched vertically to form a deeper bottom ( ) in the trench ( ). After that, the surface is planarizedby depositing an insulating film in the unfilled space of the trench ( ).

Growing community of inventors

Tokyo, Japan

Yukio Nishida