Matsushita Electric Industrial Co., Ltd.

Yukio Nakagawa

Tokikazu Matsumoto

Hideki Otaka

Takayasu Yoshida

Shinya Tanaka

Masahiro Honjo

Masao Tomita

Hidefumi Muraoka

Kazuma Morishige

Masaaki Kobayashi

Akihiro Takeuchi

Atsuo Ochi

Shinichi Aki

Seigo Fujiwara

Shinich Uchiyama

A digital data transmission apparatus and a transmission method thereof in accordance with the present invention includes a reproduction section for reproducing digital data of n (n is an integer of 2 or more) channels from a recording medium, a multiplexing section for dividing one frame in a television signal into n transmission areas on a line-by-line basis, and multiplexing digital data of the n channels reproduced by the reproduction section on the n corresponding transmission areas on the line-by-line basis, and a transmitting section for transmitting data multiplexed by the multiplexing section.

Digital data transmission apparatus and method for multiplexing multiplexing multi-channel video data within active video periods

A digital data transmission apparatus and a transmission method thereof in accordance with the present invention includes a reproduction section reproducing digital data of at least one channel from a recording medium, a multiplexing section for dividing one frame in a television signal into n transmission areas on a line-by-line basis, and a transmitting section for transmitting data multiplexed by the multiplexing section.

Digital data transmission apparatus and method for multiplexing different rate digital data within active video periods of a television signal

The receiver and transmitter/receiver in accordance with the present invention comprises a common input terminal for inputting digital data including uncompressed video data or compressed video data, a receiving circuit for carrying out serial-parallel conversion processing for the digital data from the above-mentioned common input terminal and for carrying output, an SDI decoder and an SDTI decoder for inputting data from the above-mentioned receiving circuit and for taking out the digital data including the uncompressed video data and compressed video data, respectively, a distinguishing circuit for distinguishing the transmission format of the input digital data and the presence or absence of the compression of the video data, and a selection switch for selecting data from the SDI decoder or the SDTI decoder on the basis of the result of the distinguishing of the distinguishing circuit.

Receiver and transmitter-receiver

A frequency converting circuit serves to generate a clock signal of a video sampling frequency from one of a clock signal or a sync signal outputted from a digital audio interface. An oscillator serves to generate a clock signal of the video sampling frequency. A video reference generating circuit serves to generate a video timing signal, an audio timing signal, and black burst data from one of the clock signals generated by the frequency converting circuit and the oscillator, and from an output reference video signal. In cases where the recording audio data is recorded or edited, a first switching device replaces the recording video data by the black burst data, and feeds the black burst data to the video recording processing circuit. In these cases, a second switching device replaces the video-sampling-frequency clock signal from the oscillator by the video-sampling-frequency clock signal from the frequency converting circuit, and feeds the video-sampling-frequency clock signal from the frequency converting circuit to the video reference generating circuit. In addition, a third switching device suspends detection of an output reference fed to the video reference generating circuit, and inhibits a timing reset of the video reference generating circuit.

Audio and video data synchronization apparatus for recording and

A PLL circuit for a phase comparator, a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider. A first control circuit is responsive to a discontinuous phase change of a reference signal of the PLL circuit for inhibiting the operation of the phase comparator or disconnecting the LPF from the phase comparator during a predetermined period so that the discontinuous phase change information is not transmitted through the LPF to the VCO. At the same time, a second control circuit resets the frequency divider by a pulse of the reference signal after the discontinuous phase change or applies a voltage corresponding to the discontinuous phase change to the VCO so that the output signal of the frequency divider is locked in phase to the reference signal after the discontinuous phase change. With the cooperation of the first and second control circuits, the PLL circuit quickly recovers its stable state after the discontinuous phase change of the reference signal.

Phase locked loop circuit with quickly recoverable stability

A video signal processing apparatus incorporates a 1H or 2H delay circuit, wherein H is a horizontal synchronization period. The output of the delay circuit is fed back to the input thereof so as to average the noise, thus raising the signal S/N ratio. The feedback line includes a nonlinear processing circuit which has a small gain when the signal input has a low vertical correlation, whereby the signal S/N ratio is improved without causing the delay of the color signal in the vertical direction nor the deteriorated resolution of the luminance signal.

Video signal processing apparatus

A low-range-converted chrominance signal is demodulated into two color difference signals. The two color difference signals are each filtered by a comb filter to eliminate undesired components. The two color difference signals, having been filtered, are modulated to obtain a carrier chrominance signal having a prescribed carrier frequency. To be suitable for digital signal processing, the low-range-converted chrominance signal is sampled at a first frequency which is an integral multiple of a low-range-converted carrier frequency of the low-range-converted chrominance signal when being demodulated. The two color difference signals are sampled at a second frequency which is an integral multiple of the prescribed carrier frequency of the carrier chrominance signal.

Method of reproducing a chrominance signal from a previously

A chrominance signal processing apparatus for converting an input carrier chrominance signal received in a first operation mode to an output low-band converted chrominal signal, and for converting an input low-band converted chrominance signal received in a second operation mode to an output carrier chrominance signal includes a frequency converting circuit which performs these conversions in the respective first and second operation modes. A carrier chrominance signal carrier and a low-band converted chrominance signal carrier, both for use in the frequency converting circuit, are respectively generated by the first and second carrier generating circuits. In each of the first and second operation modes, one of the first and second carrier generating circuits is controlled to compensate for a phase error of each of the input signals. A phase error detecting circuit detects the phase error from the burst signals extracted from the output and respectively input low-band converted chrominance signals in the first and second operation modes to produce a control voltage signal for controlling the first or second carrier generating circuit. Control signals for the ACC and color killer circuit are also produced from the abovenoted burst signals.

Chrominance signal processing apparatus

A chrominance signal processing system includes a variable gain amplifier capable of effecting gain control for amplifying a carrier chrominance signal and an A/D converter for effecting an analog/digital conversion of an output of the variable gain amplifier. A demodulator demodulates an output of the A/D converter into two chrominance signals on two demodulation axes which are apart by 90.degree. from each other. One of the chrominance difference signals is disposed at a right angle with respect to a vector of a burst signal of the carrier chrominance signal and the number of bits of the two chrominance difference signals are chosen such that the number of bits of the one chrominance difference signal disposed at right angles with respect to the burst signal vector is smaller than the number of bits of the other of the two chrominance difference signals. A computing circuit computes an amplitude of the burst signal from the two chrominance difference signals and a gain control circuit produces a circuit for controlling the gain of the variable gain amplifier from the output of the computing circuit. The two chrominance difference signals may be the R-Y and B-Y signal components of a carrier chrominance signal.

Growing community of inventors

Moriguchi, Japan

Yukio Nakagawa