Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Toyo Ink Mfg. Co., Ltd.

Yukio Kodama

Kazuo Murakami

Narihiro Matoba

Masaru Ohnishi

Yoshifumi Imanaka

Masaaki Tanioka

Hiroaki Furuta

Eisaku Tomita

Hideo Yoshida

Kenichi Fujita

Takehiko Umeyama

Takehisa Mizuguchi

Satoshi Okutsu

Hideki Miyake

Ichiro Toyoda

Masahiro Deguchi

Masashi Sawamura

Tetsuji Fujisaki

Yuji Hirasawa

Takeshi Kyomoto

It is an object to provide a technique that can enhance data rewriting tolerance. An information processing apparatus includes a first nonvolatile memory and a second nonvolatile memory. The first nonvolatile memory stores first data. The second nonvolatile memory stores second data that is higher in update frequency than the first data. This allows the data rewriting tolerance in the device to be enhanced. For example, data of a dynamic map that is a dynamically changeable map can be applied to at least the second data among the first data and the second data.

Information processing apparatus and information processing method

A colored composition for color filter contains a colorant carrier formed of a transparent resin, a precursor of a transparent resin or a mixture thereof, and a green colorant dispersed in the colorant carrier. The green colorant contains a first halogenated metallophthalocyanine pigment having copper as a central metal, and at least one second halogenated metallophthalocyanine pigment having, as a central metal, a metal selected from the group consisting of Mg, Al, Si, Ti, V, Mn, Fe, Co, Ni, Zn, Ge and Sn. The content of the second halogenated metallophthalocyanine pigment is within a range of 1 to 80 mol % based on a total amount of the green colorant. Also disclosed is a color filter including at least one red filter segment, at least one blue filter segment, and at least one green filter segment. At least one green filter segment is prepared from the above-mentioned colored composition.

Colored composition for color filter and color filter

An error control apparatus includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes, which is to be interleaved in accordance with a predetermined interleaving order; a first cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.

Error control apparatus and method using cyclic code

A line buffer device temporarily stores a predetermined area of original image data which are divided into small blocks, each having a small area, so as to encode the image data for each block into data having a fixed length by a compression processor. The line buffer device is composed of a first-stage line buffer group and a second-stage line buffer group. The number of line buffers in the first-stage line buffer group is smaller by one than the number of lines constituting one block and the number of line buffers in the second-stage line buffer group is the same as the number of lines constituting one block. Encoding processing time is shortened and the circuit structure is simplified.

Image data compression-expansion circuit

When encoding data received by a dividing circuit and to be included in a CRC code word, the data is divided by a generator polynomial and remainder data resulting from the division is output from a plurality of parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value and '0' information in the adder to produce a sum. The sum is a CRC code for a CRC code word to be transmitted. When detecting code errors, data from a CRC code word is received by the dividing circuit, where the data is divided by the generator polynomial, and remainder data resulting from the division is output from the respective parallel data output terminals. The remainder data is added to the CRC intrinsic value and CRC code in the adder to produce a sum, and the sum is processed by a logical sum circuit to produce a logical sum output as a CRC flag. The CRC code generation and code error detection circuit generates CRC codes to be included in CRC code words at high speed and detects errors in received CRC code words at high speed.

CRC code generation circuit, code error detection circuit and CRC

A Cyclic Redundancy Check (CRC) code word except a fixed pattern is provided to a code data input terminal of a division circuit in synchronization with a clock signal and divided at the division circuit, then, a remainder data of the division result is outputted from output terminals. The remainder data outputted from the output terminals is compared with a CRC inherent value at a comparison circuit, and a comparison result signal indicating whether the CRC code word includes errors is outputted. A temporary memory means takes in the comparison result signal in response to rise of a clock signal inputted into a clock signal input terminal, temporarily stores it, then output its storage contents as an error detecting signal via an output node.

Code error detecting circuit

When encoding data bits in a CRC code word and '0' information is received for every bit by a dividing circuit, the CRC code word is divided by a generation polynomial and remainder data resulting from the division is output from parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value in the adder to produce a sum. The sum is a CRC code in a CRC code word for transmission. When a code error is detected, data having a plurality of bits in a CRC code word and a CRC code are received by the dividing circuit, where they are divided by the generation polynomial and remainder data is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder to produce a sum, and the sum is processed into a logical sum in a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.

CRC code generation circuit, code error detection circuit, and CRC

When encoding, data bits in a CRC code word are received for every bit by a dividing circuit where the CRC code word is divided by a generation polynomial and a remainder is output from parallel data output terminals. The remainder is added to a CRC intrinsic value and '0' information in the adder. The addition result is a CRC code in a CRC code word for transmission. When a code error is detected, data bits in a CRC code word and a CRC code are received for every bit by the dividing circuit, where they are divided by the generation polynomial and a remainder is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder, and the result is further processed by a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.

CRC code generation circuit for generating a CRC code and a code error

An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.

Error correction circuit

In a sampling mode, a servo signal sampling and holding switch (4.sub.a) and a reference voltage sampling and holding switch (30.sub.a) are turned off, so that transistors (Q.sub.7a, Q.sub.5a) are turned on. In response to on states of the transistors (Q.sub.7a, Q.sub.5a), capacities (C.sub.3a, C.sub.30a) are charged with the peak voltage (V.sub.ref +(1/2)V.sub.s) of a servo signal and a reference voltage (V.sub.ref), respectively. In a holding mode, the sampling and holding switches (4.sub.a, 30.sub.a) are turned on, so that the transistors (Q.sub.7a, Q.sub.5a) are turned off. the charging voltages (D, E) of the capacitors (C.sub.3a, C.sub.30a) are discharged through post-stage buffers (5.sub.a, 3.sub.a), so that they include offsets which are canceled through a subtractor (6.sub.a).

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Tokyo, Japan

Yukio Kodama