Tokyo Shibaura Denki Kabushiki Kaisha

Yukio Kitagawa

Yoshiaki Moriya

Ichiro Kobayashi

In a data processing apparatus including an instruction register and an instruction decoder connected therewith, when a designation instruction (operand changing instruction) is set in the instruction register, the operand (the code of source or destination) of the designation instruction is registered in a source address register or a designation address register connected to the instruction register through a gate circuit. The registers produce control signals through decoders respectively for selecting predetermined operands. When the designation instruction is decoded by the instruction decoder a first (for source) and a second (for destination) flip-flop circuits which are connected to the output terminal of the instruction decoder are set. The outputs of these flip-flop circuits are applied to the negative input of an AND gate circuit connected to the instruction decoder. When an instruction to be executed subsequent to the designation instruction is decoded by the instruction decoder, the instruction decoder produces a control signal that selects the operand of the instruction, but this control signal is selectively blocked by the AND gate circuit, with the result that the operand designated by the designation instruction is substituted by the operand of the instruction to be executed subsequently.

Data processing apparatus

An instruction outputted from an instruction register is decoded by an instruction decoder. In the instructions decoded by said instruction decoder, a subroutine call instruction of which the address field is coded is applied to a data converter of which the address field is connected to said instruction register. The data converter decodes the inputted and coded address to produce a given effective address.

Data processing device using a subroutine call instruction

A memory address designating system comprising a program counter and data counter for holding the addresses of an instruction word area and data area respectively of a memory, an increment/decrement counter for modifying the address, and gate circuits for controlling data transfer between the program counter, data counter and increment/decrement counter, in which, when the memory is accessed by the addresses of the instruction word area and data area of the memory, an address held in the program counter is modified by an increment/decrement counter and consequently is incremented by one and sent through a gate to the data counter where it is held. On the other hand, the address of the data area held in the data counter is supplied through a gate to he program counter and then to the increment/decrement counter where it is modified. At the same time, the data of the data area of the memory is fetched and the modified address is supplied to the data counter while the modified address stored in the data counter is supplied to the program counter.

Memory address designating system

Two flip-flops for carry information are provided in a data processor; one for carry of arithmetic operation and the other for carry occuring when a program counter is incremented. A state of the latter flip-flop provides a condition of a conditional branch instruction. With the provision of those flip-flops, a multidigit operation can be performed without increasing programsteps to save carry information attendant on the operation data. A simple program may be prepared without increasing hardware for skip instruction processing.

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Yokohama, Japan

Yukio Kitagawa