Kabushiki Kaisha Toshiba

Yukio Kawase

Teruo Uemura

A semiconductor memory device comprises a non-volatile memory cell array having a plurality of memory cells, enhancement type load transistors having a threshold voltage, and at least one peripheral circuit, such as level shifters, a column decoder, etc., including enhancement type transistors having a threshold voltage. For increasing the writing speed of the memory cells, the threshold voltage of the enhancement type load transistors is set so that it is different from that of the enhancement type transistors of the peripheral circuit. For example, the threshold voltage of the enhancement type load transistors is lower than that of the enhancement type transistors of the peripheral circuit.

Growing community of inventors

Yokohama, Japan

Yukio Kawase