Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Lapis Semiconductor Co., Ltd.

Yukio Kawamura

A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.

Power-on reset circuit

An inverter circuit includes a first transistor connected between an input terminal and a gate of a second transistor, a second transistor connected between power supply voltage and an output terminal, a third transistor connected between an input terminal and a gate of a fourth transistor and a fourth transistor connected between a ground and the output terminal.

Inverter circuit having an improved slew rate

The Phase Locked Loop circuit of this invention has both a short locking time and a stable operation. This Phase Locked Loop circuit has two phase comparators. The inputs to these two comparators are a reference signal V and a feedback signal V . The first phase comparator has two separate outputs depending on the phase difference &dgr; between the signals V and V . The first output is a signal up when &dgr; is smaller than &minus;&tgr;1, and the second output is a signal dn when &dgr; is larger than &minus;&tgr;1. The second phase comparator also has two outputs depending on the phase difference &dgr; between the signals V and V . The first output is a signal up when &dgr; is smaller than &minus;&tgr;2 (&tgr;2>&tgr;1), and the second output is a signal dn when &dgr; is larger than &tgr;2. The signals up and up are output when the &dgr; has positive polarity and large absolute value. When &dgr; has positive polarity and a small absolute value, only signal up is output. Signals dn and dn are output when &dgr; has negative polarity and large absolute value. When &dgr; has negative polarity and a small absolute value, only signal dn is output. The voltage control oscillator outputs an oscillation signal V . The frequency of the signal V rises or falls in accordance with the polarity of &dgr;. Additionally, the frequency of the signal V is controlled in accordance with the absolute value of the phase difference &dgr;.

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Miyazaki, Japan

Yukio Kawamura