Kabushiki Kaisha Toshiba

Yukio Ishikawa

Kenji Sakaue

Toshihiko Kitazume

Teruyuki Matsuoka

Fuying Yang

Hironori Uchikawa

Tatsuyuki Ishikawa

Kazuhiro Ichikawa

Tsuyoshi Ukyo

Tsuyoshi Ukyou

According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than '2', by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1&#x3c;=s&#x3c;t). The search processing unit calculates the root of the error position polynomial, with a concurrency of computation being '1', when the number of error bits exceeds the predetermined value s.

Error correction device and error correction method

According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.

Error detecting device and memory system

A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.

Semiconductor memory device, semiconductor memory system, and erasure correction method

An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability &#x3b2; in association with each first address, a check node storage section that stores TMEM variables to calculate an external value &#x3b1; in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Growing community of inventors

Yokohama, Japan

Yukio Ishikawa