Fujitsu Corporation

Yukio Furukawa

Akihiko Takada

Hisakazu Ohmori

Masakazu Oi

Kazuo Wani

Kohichi Ohno

A clock change circuit contains: a clock gate unit for receiving first and second clock signals, and detecting a timing at which both the first and second clock signals are at an inactive level to output an active timing signal indicating the timing; a delay unit for inputting a select control signal and the timing signal, and outputting a delayed select control signal the state of which is changed to the same state of the select control signal after the active timing signal is received from the clock gate unit; and a select unit for inputting the first and second clock signals, and selects one of the first and second clock signals according to the delayed select signal to output the selected clock signal.

Clock change circuit preventing spike generation by delaying selection

An apparatus for receiving at a master station signals from a plurality of slave stations connected by a bus and then reproducing the data, wherein use is made of a single clock generating source of a fixed phase so as to simplify the apparatus, provision being made of a data/clock relative delay unit which gives a variable relative delay between the fixed phase clock and the received data signal received by the master station in accordance with the phase difference between a transmitted frame timing pulse (TF) from the master station and the received frame timing pulse (RF) received from the slave stations.

Apparatus for reproducing received data

An undershoot eliminating circuit is provided between a pulse transformer of a pulse transmitter coupled to a transmission line and a pulse transformer driving circuit for driving the pulse transformer. The pulse transformer driving circuit has an impedance high enough to cause the pulse transmitter to be substantially isolated from the transmission line. The undershoot eliminating circuit includes a capacitor, and a switching unit. The switching unit is connected to the capacitor, and has the function of selectively connecting the capacitor to the pulse transformer driving circuit and the pulse transformer in parallel on the basis of a voltage based on a pulse wave generated by the pulse transformer driving circuit and applied across the switching unit.

Pulse transmission circuit with undershoot eliminating circuitry

A polarity detector for subscriber lines in a data transmitting system which detects the polarity of 2-wire subscriber lines using 2B1Q codes. A converter converts a quaternary 2B1Q code into binary code and outputs complementary binary data. A frame synchronizing signal detector detects a binary code frame synchronizing signal in the complementary binary data and outputs a timing signal. A pattern detector detects an all '1's or '0's state of the complementary binary data and the timing signal. A selector circuit selects all complementary data having a single polarity in response to all '1's or '0's detected by the pattern detector. Therefore, correct data is received by correctly detecting the polarity of the subscriber line.

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Kawasaki, Japan

Yukio Furukawa