Canon Kabushiki Kaisha

Yukio Araoka

Daisuke Kobayashi

Toshiaki Ono

Yoichiro Handa

Yuichi Naito

Kentaro Tsukida

Satoru Shingai

A solid-state imaging device includes a plurality of pixels arranged in a matrix, wherein one pixel of the plurality of pixels is arranged in one unit pixel region of a plurality of unit pixel regions, a plurality of sub vertical output lines, each of which outputs pixel signals from the plurality of pixels in the same pixel column, and a plurality of block select circuits provided in one-to-one correspondence with the plurality of sub vertical output lines. A load capacitance connected to a main vertical output line is reduced by connecting the plurality of sub vertical output lines and the main vertical output line via the plurality of block select circuits. This makes high-speed pixel signal readout possible.

Solid-state imaging device and imaging system

In a photoelectric conversion apparatus, a signal generation circuit includes an amplification unit which generates a reference signal and which is configured the same as amplification units included in pixel output circuits, and a signal based on a reference signal is supplied to input nodes of a plurality of signal processing circuits or input nodes of a plurality of signal output circuits.

Photoelectric conversion apparatus and photoelectric conversion system including pixels which generate signals by performing photoelectric conversion on incident light

Solid-state imaging device and imaging system having a plurality of unit pixel regions

A solid state imaging device includes a pixel circuitconfigured to generate a pixel signal by photoelectric conversion, a reference signal generation circuitconfigured to generate a reference signal which changes in level with time, and a plurality of comparators configured to, based on the reference signal generated by the reference signal generation circuit, compare a plurality of reference signals being given offset voltages differing from each other, with the pixel signal, or compare a plurality of pixel signals being given offset voltages differing from each other, with the reference signal.

Solid state imaging device and method of driving solid state imaging device

An imaging apparatus includes: pixel circuits () arranged in a matrix, each configured to generate a pixel signal by photoelectric conversion; readout circuits () each provided correspondingly to each column of the plurality of pixel circuits, and each configured to read out the pixel signals from the pixel circuits of a corresponding column; 2n first output lines (-to-) to which output terminals of every 2n columns of the readout circuits are commonly connected; and an adding unit configured to add the pixel signals from the pixel circuits arranged in different columns. Among the readout circuits on plural columns connected to the pixel circuits which are subjected to adding by the adding unit, only the readout circuit on one column performs the read out, and all of the 2n first output lines receives input of the pixel signals from one of the plural readout circuits.

Imaging apparatus including readout circuits and output lines, and driving method thereof

A scanning circuit includes a first shift register including a plurality of registers and being operable to specify a register where scanning is skipped among the plurality of registers, and a second shift register adapted to transmit skip information for specifying the register to be skipped.

Scanning circuit, photoelectric conversion apparatus, and image pickup system for specifying a register where scanning is skipped among a plurality of registers

A photoelectric conversion system is configured to correct a difference in offset component of signals to be outputted per photoelectric conversion device.

Photoelectric conversion system

An image sensor has a pixel array, a readout portion configured to read out a signal from the pixel array, and a control portion which controls the readout portion. The readout portion includes a row selecting portion which selects a row in the pixel array, a column selecting portion which selects a column in the pixel array, and an output portion which outputs a signal from a pixel, of pixels on a row selected by the row selecting portion, which corresponds to a column selected by the column selecting portion. The pixel array includes blocks differing in distance from the output portion, and the control portion controls readout periods required by the readout portion to read out signals from the blocks so as to read out signals from blocks in longer readout periods as distances from the output portion increase.

Image sensor, imaging system, sensor, and operation method for image sensor

Each of pixels in a pixel array includes a photoelectric converter and a readout circuit which outputs a signal in accordance with charges generated in the photoelectric converter. The readout circuit includes a group of transistors which are disposed so as to form a current path fed by a current source. The readout circuit of a pixel in a first line in the array and the readout circuit of a pixel in a second line in the array are disposed between the photoelectric converter of the pixel in the first line and the photoelectric converter of the pixel in the second line. Directions of currents respectively flowing through the group of transistors in the readout circuit of the pixel in the first line and the plurality of transistors in the readout circuit of the pixel in the second line are the same.

Solid-state image sensor

A solid-state image sensor comprising a pixel array having a plurality of pixels, and a plurality of signal processing circuits each of which amplifies a signal of the pixel array, wherein each of the plurality of signal processing circuits comprises an operation amplifier having an input terminal and an output terminal, an input capacitance arranged between the input terminal and the column signal line, and a feedback circuit which connects the input terminal with the output terminal, wherein the feedback circuit is configured to form a feedback path in which a first and a second capacitance elements are arranged in series in a path connecting the input terminal to the output terminal, and a third capacitance element is arranged between a reference potential and a path connecting the first capacitance element to the second capacitance element.

Growing community of inventors

Hiratsuka, Japan

Yukio Araoka