Kabushiki Kaisha Toshiba

Tosbac Computer System Company Limited

Yukinori Uchino

Yasunori Tanaka

Toshikazu Sei

Muneaki Maeno

Yutaka Tanaka

Hiroaki Suzuki

Nobuaki Otsuka

Shinji Fujii

Toshiaki Mori

Yasunobu Umemoto

Yoshiaki Hashiba

Hideo Hashimoto

Izumi Sakai

A semiconductor device of an aspect of the present invention comprises a package substrate, one first power supply terminal provided on the package substrate, one second power supply terminal provided on the package substrate, a semiconductor chip disposed on the package substrate, first and second internal power supply circuits provided in the semiconductor chip, one first ESD protection element which is provided in the first internal power supply circuit and which is connected to the first power supply terminal, and a plurality of second ESD protection elements, the second ESD protection elements being provided in the second internal power supply circuit, the size of one second ESD protection element being smaller than that of the first ESD protection element, the second ESD protection elements being connected to the common second power supply terminal.

Semiconductor device with different sized ESD protection elements

A level shifter circuit converts a signal generated by an internal circuit which operates with a first power supply, into a signal by a second power supply having voltage higher than that of the first power supply. The voltages at substrate terminals of two NMOS transistors, to which complementary two signals by the first power supply are input, is boosted to voltage higher than circuit ground potential in a period in which a voltage level of one of the two input signals and a voltage level of an output signal by the second power supply do not coincide with each other.

Level shifter circuit

A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.

Semiconductor device provided using wiring data of common design core

A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.

Master slice LSI and layout method for the same

The present invention relates to the improvement in the degree of on-chip integration of memory cells utilizing a gate array layout. A plurality of three-transistor DRAM cells are disposed on a semiconductor chip implementing a regular cross-point array, each DRAM cell is made up of two nMOS transistors and one pMOS transistor formed in one basic cell. The semiconductor chip disposes therein nMOS memory-cell blocks and pMOS memory-cell blocks alternately, effectively utilizing the gate array layout.

Gate array LSI

In an integrated circuit device using a plurality of different power supply voltages, the application of an input voltage exceeding the power supply voltages to an input/output circuit is prevented. When a p-type substrate is used, a plurality n-wells are formed to surround an integrated circuit region on a central portion of the substrate. When an n-type substrate is used, a plurality of p-wells are formed in the same manner. A predetermined power supply voltage is applied to each well to select transistors of the input/output buffer in accordance with the voltage level of an external voltage.

Semiconductor input/output circuits operating at different power supply

A signal output circuit device according to the present invention comprises a first MOS transistor whose conduction is controlled by the potential given to its gate terminal, and gives the high level potential that is supplied by a high level voltage source to the output terminal, a diode which is inserted between the high level voltage source and the first MOS transistor so as to have its forward direction in the direction from the high level voltage source to the first MOS transistor, a second MOS transistor whose conduction is controlled by the potential given to its gate terminal, and supplies the low level potential supplied by a low level voltage source to the output terminal, and a diode which is inserted between the low level voltage source and the second MOS transistor so as to have its forward direction in the direction from the second MOS transistor to the low level voltage source.

CMOS output circuit device

A read only semiconductor memory device which comprises a plurality of transistor pairs comprising two transistors of one and the other conductivity types arranged in a matrix manner, thus allowing only one of the two transistors constituting each transistor pair to be operated to obtain a predetermined logical output. By employing a structure of the transmission gate type as the transistor pair, high speed and reliable operation for raising a potential on the output line can be realized.

Growing community of inventors

Yokohama, Japan

Yukinori Uchino