Kabushiki Kaisha Toshiba

Yukinori Muroya

Shigeru Atsumi

Kimiyoshi Usami

Naoka Yano

A latch circuit receives complementary signals and consists of an nMOS transistor whose source is connected to an input terminal of the latch circuit and a series-connected circuit consisting of first and second pMOS transistors arranged between and connected to a drain terminal of the nMOS transistor and a high-potential power supply. The complementary signals are a first signal and a second signal that is an inversion of the first signal. Each of the signals has a pulse characteristic that rising time is longer than falling time. The latch circuit latches a quick fall by passing the first signal through the nMOS transistor. On the other hand, the latch circuit latches a slow rise by turning on the second pMOS transistor in response to a fall in the second signal.

Latch circuit and arithmetic unit having the same

Sense amplifier output circuit used in semiconductor memory devices

A memory cell is provided for use in a multi-port RAM. In addition to a flip-flop circuit for memorizing data and a transfer gate for transmitting data into the flip-flop, at least a transistor series having a first, a second, and a third field effect transistors are provided. These transistors are series connected between a bit line of said RAM and a low electric supply so as to read out data from said flip-flop circuit within a short period.

Growing community of inventors

Yokohama, Japan

Yukinori Muroya