Renesas Electronics Corporation

Renesas Technology Corp.

Renasas Electronics Corporation

Yukinori Akamine

Satoshi Tanaka

Koji Maeda

Taizo Yamawaki

Manabu Kawabe

Hiroshi Kamizuma

Kazuo Watanabe

Akio Yamamoto

Masumi Kasahara

Kazuaki Hori

Kazuyuki Hori

Sungwoo Cha

Yasuo Shima

Ryoichi Takano

Takashi Yano

Masahiro Ito

Takao Okazaki

Yasuyuki Kimura

Kazuhiko Hikasa

Hirotake Ishii

Takayasu Norimatsu

Hisayoshi Kajiwara

Irei Kyu

The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Semiconductor integrated circuit and circuit operation method

The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90&#xb0; plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90&#xb0; on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Transceiver

The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

Transmitter and semiconductor integrated circuit available for it

The semiconductor integrated communication circuit includes: a low-noise amplifier; a receive mixer; a receive VCO; a demodulation-processing circuit; a modulation-processing circuit; a transmit mixer; a transmit VCO; a second-order-distortion-characteristic-calibration circuit; a quadrature-receive-signal-calibration circuit; and a test-signal generator. The test-signal generator generates first and second test signals using the transmit VCO. In the second-order-distortion-characteristic-calibration mode, the second-order-distortion-characteristic-calibration circuit variably changes an operation parameter of the receive mixer thereby to calibrate the second-order distortion characteristic to achieve its best condition while the first test signal is supplied to the receive mixer. In the quadrature-receive-signal-calibration mode, the quadrature-receive-signal-calibration circuit calibrates IQ mismatch of a quadrature receive signal to achieve the best condition thereof while the second test signal is supplied to the receive mixer. The integrated communication circuit can minimize the increase in chip footprint of a test-signal-generating circuit used to perform calibrations of both the second-order characteristic and IQ mismatch.

Semiconductor integrated communication circuit and operation method thereof

A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.

This invention provides a wireless transmitter circuit for mobile communication apparatus and this circuit can be configured with fewer components and is suitable for downsizing. A single PLL synthesizer serves as both RF frequency band PLL and IF frequency band PLL among three oscillators for TX, RX and IF frequency bands, which have been required in conventional mobile communication apparatus. The number of necessary oscillators occupying a large area within a chip is reduced and the number of components is decreased. Specifically, circuitry is arranged to generate local oscillation signals for RF and IF frequency bands by frequency dividing the output of a VCO of the RF frequency band PLL.

Wireless transmitter circuit and transceiver using the same

A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block. Increase in the number of voltage-controlled oscillators for multiband communication, broadening of the band, and increase in phase noise can be reduced.

When generating an RF test signal for mismatch calibration for receiver in order to calibrate reception mismatch of an I-phase signal and a Q-phase signal that are output from demodulated signal processing circuits coupled to mixers for receiving, a Tx VCO avoids covering the higher frequency of an RF received signal in an FDD system. An RF test signal generating unit generates, in a calibration mode of a mismatch calibration for receiver circuit, the RF test signal by using an oscillation output signal of the Tx VCO and other circuits, and supplies the same to the mixers for receiving via a switch. The RF test signal has a frequency within an RF reception frequency band that is higher than that of an RF transmission signal with the maximum frequency band of multiband radio frequency communications. By switching the switch in a reception mode, an output of a low-noise amplifier that amplifies the RF received signal received by an antenna is supplied to each of the mixers for receiving.

Integrated circuit and device for mobile communications

In conventional polar-loop transmitter circuits, using two feedback circuits intended to control the amplitude in an open loop and phase of a power output in closed loop, respectively, during transmission, causes current consumption to increase during delivery of a small power output. Therefore, a complex table has to be prepared in order to correct the nonlinearities in the amplitude-to-amplitude characteristic of the power amplifier and the amplitude-to-phase characteristic thereof. In order to reduce the current consumption required for the delivery of a moderate or small power output, a polar-loop transmitter circuit in which two feedback circuits intended to control the amplitude and phase of the power output respectively are active when the power amplifier delivers a large power output exhibiting strong nonlinearity, and when the power amplifier delivers a moderate or small power output, the amplitude of the power output is controlled in the open loop.

Transmitter circuits and apparatus of wireless application

In a direct conversion receiver, to cancel a DC offset generated in the baseband processing block, negative feedback arrangements comprising a gain control amplifier and a low-pass filter are respectively attached to the I and Q signal branches of the baseband block following mixer outputs. The gain control amplifier in each negative feedback circuit is gain adjusted so that the product G&#xb7;B of the gain G of a primary gain control amplifier and its own gain B will be constant and thereby the DC offset is cancelled. This DC offset cancellation can be applied in a continuous receiving system with no intermittent time during a receiving operation. Capacitance elements located off-chip can be reduced to those to be used only in the low-pass filters in the negative feedback circuits, whereas many off-chip capacitance elements have been required to be inserted between each stage of gain control amplifiers in conventional baseband chains.

Direct conversion receiver

The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Phase locked loop circuit

The receiver, which enables rejection of image signals with higher accuracy over wider frequency band, can be provided as a low IF receiver by inputting a calibration signal of frequency f(1&#x2266;i&#x2266;N) before reception of signals and determining the frequency response f(z) to f(z) of a calibrating filter in a filter mismatch calibrating circuit (FIL_CAL)to make zero amplitude and phase mismatches between the I component and Q component of the quadrature demodulation signal at the frequency f.

Growing community of inventors

Kokubunji, Japan

Yukinori Akamine