Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Yukinobu Adachi

Masaki Tsukude

Masanori Hayashikoshi

Katsuhiro Suma

Susumu Tanida

Hiroshi Akamatsu

Hiromi Okimoto

Tooru Ichimura

In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.

Dynamic semiconductor memory device and method of testing the same

An external power source voltage Vcc rises until it exceeds the threshold voltage Vth of an NMOS transistor diode-connected between the external power source (voltage Vcc) and an internal boosted power source (voltage Vpp), whereupon the NMOS transistor is turned on, supplying the internal boosted power source with a voltage (Vcc-Vth) until the power source voltage Vcc reaches its final value. And when the internal reset signal ZPOR expires, the internal boosted power source generating circuit is started to operate so that the internal boost source voltage Vpp is boosted to an intended level Vpp. As a result, when the power is turned on, early stabilization of the boosted power source voltage is realized in a semiconductor storage device.

Semiconductor storage device requiring short time for program voltage to

Fluctuation of the minimum voltage value allowing determination of the 'H' level of an input signal and of maximum voltage value allowing determination of the 'L' level of the input signal dependent on the supply voltage is suppressed, in order to enlarge operation margin. A semiconductor integrated circuit device includes a P channel transistor and an N channel transistor constituting a CMOS inverter, an N channel transistor connected in parallel to N channel transistor, and a plurality of N channel transistors for applying a voltage provided by lowering the supply voltage to the gate electrode of N channel transistor, in which a plurality of N channel transistor are connected in series.

Semiconductor integrated circuit device

In response to an external control signal, a first timing detecting circuit and a high voltage detecting circuit detect setting of a signature mode and provide a signature mode signal to a second timing detecting circuit. The second timing detecting circuit outputs an output buffer activating signal to the output buffer in response to the external control signal. In response to the output buffer activating signal, the output buffer detects an internal supply voltage and provides the same to an external pin.

Semiconductor device allowing accurate characteristics test

An improved DRAM includes a main circuit and an output driver circuit, respectively, energized by externally applied two power supply voltages. The DRAM includes a timing coinciding circuit for making the supply-timing of the two power supply voltages to the circuits coincided to each other. When power supply voltage only is applied, output driver circuit has a tendency to consume an excessive penetrating current in response to an unstable output signal provided from main circuit. Even though the two power supply voltages are applied in different timing, the excessive current consumption in the output driving circuit is avoided, since timing coinciding circuit simultaneously starts and ends the supply of output power supply voltages.

Growing community of inventors

Hyogo, Japan

Yukinobu Adachi