Sharp Kabushiki Kaisha Corporation

Yukimine Shimada

Hirohiko Nishiki

Kenichi Kitoh

Tohru Senoo

Atsushi Ban

Tetsunori Tanaka

Wataru Nakamura

Mikiro Okada

Koji Imura

A semiconductor device is provided with an oxide semiconductor thin-film transistor (TFT); a calibration electrode that is positioned so as to face an oxide semiconductor layer with an insulating layer therebetween, and, when viewed from the direction of the substrate normal line, overlaps at least part of a gate electrode with the oxide semiconductor layer interposed therebetween; and a calibration voltage setting circuit that determines the voltage to be applied to the calibration electrode. The calibration voltage setting circuit is provided with: a monitor TFT that is configured using a second oxide semiconductor layer, which is substantially the same as the oxide semiconductor layer of the oxide semiconductor TFT; a detection circuit that is configured so as to be able to measure the device characteristics of the monitor TFT; and a voltage determination circuit that determines the voltage to be applied to the calibration electrode on the basis of the measured device characteristics.

Semiconductor device and display device

This semiconductor device () includes: a substrate (); a thin-film transistor () which includes an oxide semiconductor layer () as its active layer; a protective layer () covering the thin-film transistor; a metal layer () interposed between the protective layer () and the substrate (); a transparent conductive layer () formed on the protective layer (); and a connecting portion () to electrically connect the metal layer () and the transparent conductive layer () together. The connecting portion () includes an oxide connecting layer () which is formed out of a same oxide film as a oxide semiconductor layer () and which has a lower electrical resistance than the oxide semiconductor layer (). The metal layer () is electrically connected to the transparent conductive layer () via the oxide connecting layer ().

Semiconductor device and method for manufacturing same

An active matrix substrate () of the present invention includes a substrate, a gate line () formed on the substrate, and an interlayer insulating layer () for insulating a layer formed on the gate line () from the gate line (). In a region of the substrate, the interlayer insulating layer () is not provided on an upper surface of the gate line (), and therefore, the upper surface is exposed. On the other hand, the insulating layer () is provided on the substrate so as to have contact with at least an edge face of the gate line () which edge face is on an extension of a longitudinal direction of the gate line ().

Active matrix substrate, method for manufacturing same, and liquid crystal display apparatus

A semiconductor memory device according to the present invention includes: a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n &lt;2.sup.n +m&lt;2.sup.n+1 ; an address decoder for receiving an address signal of (n+l) bits and for specifying one of the (2.sup.n +m) memory cells in accordance with the address signal; an output circuit for outputting data stored in the memory cell specified by the decoding means; an empty address detecting circuit for receiving at least two bits of the address signal of (n+1) bits and for generating a detection signal which indicates whether the address signal represents an empty address or not; and a control circuit for receiving an enable signal and for generating a control signal for outputting the data stored in the specified memory cell in accordance with the enable signal, wherein the control circuit further receives the detection signal and generates a control signal for inhibiting the data from being output when the address signal specifies an empty address, regardless of the state of the enable signal.

Growing community of inventors

Osaka, Japan

Yukimine Shimada