Kioxia Corporation

Yukimasa Miyamoto

Tomoya Horiguchi

Daisuke Taki

Takeshi Kumagaya

A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Information processing system and memory system

A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L&#x3c;N, where L=N&#xd7;Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Growing community of inventors

Kanagawa, Japan

Yukimasa Miyamoto