Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Yukimasa Miyamoto

Shinichi Kanno

Masaya Tarui

Taku Ohneda

Riku Ogawa

Kosuke Hatsuda

Koichi Nagai

Kohei Oikawa

Masahiro Sekiya

Shuou Nomura

Kojiro Suzuki

Shoji Sawamura

Kazuki Inoue

Toru Katagiri

Taku Ooneda

According to one embodiment, a memory system is connectable to a host device including a first memory. The memory system includes a memory controller and a second memory in which data from a host device is stored. The memory controller includes a third memory, a first unit and a second unit and has a first space. The first unit designates a first address in the first space. The second unit converts, by using a conversion table, the first address into a second address in a first area of the first memory. The conversion table includes a plurality of layers and includes a first conversion table of a top layer and a second conversion table of a layer lower than the first conversion table. The first conversion table is stored in the third memory. The second conversion table is stored in a second area of the first memory.

Memory system which uses a host memory

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller reads write data associated with a first write command from a host memory by a unit of a first size in response to the first write command from a host. The host memory is included in the host. In a case where the size of first data not yet read from the host memory out of the write data is less than a second size, in response to a second write command, the controller reads second data of the second size and writes the read second data into the nonvolatile memory. The second data includes the first data and third data included in write data associated with the second write command. After writing the second data into the nonvolatile memory, the controller transmits a notice for the first write command to the host.

Memory system and method

According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.

Semiconductor apparatus, routing module, and control method of semiconductor apparatus

According to one embodiment, a wireless communication apparatus includes a reception unit, a storage unit, a transfer amount decision unit, and a first transfer control unit. The reception unit receives a first frame with a frame length of a first length using a first wireless method. The storage unit stores the first frame. The transfer amount decision unit sets, when a second length decided based on the first wireless method is smaller than the first length, a third length to be the second length, and sets, when the second length is not less than the first length, the third length to be a value not more than the first length. The first transfer control unit transfers transfer information including first information of the third length in the first frame to a first memory, and transfers the first frame by the first length to a second memory.

Wireless communication apparatus and wireless communication method

A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

Logic circuit system and method of changing operating voltage of a programmable logic circuit

A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.

Logic circuit apparatus for selectively assigning a plurality of circuit data to a plurality of programmable logic circuits for minimizing total power while maintaining necessary processing performance

A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

Logic circuit apparatus and timeshare operating method of a programmable logic circuit

A logic circuit system, having a programmable logic circuit including a circuit configuration including a first set of plural unit circuits and that is reconfigurable during operation, a circuit configuration information supplier configured to supply circuit configuration information about a second set of plural unit circuits to said programmable logic circuit, a change controller configured to change the circuit configuration of said programmable logic circuit from said first set of said plural unit circuits to said second set of said plural unit circuits based on said circuit configuration information, an operation time measurer configured to measure operation times of said first and second set of plural unit circuits, and a clock-and-voltage supplier configured to use said measured operation times to change from a first frequency and voltage value corresponding to said first set to a second frequency and voltage value corresponding to said second set, and to supply a clock signal having said second frequency and voltage value to said programmable logic circuit, thereby varying a programmable logic circuit frequency and voltage value in accordance with variations in said operation times.

Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.

Method and apparatus for selectively assigning circuit data to a plurality of programmable logic circuits for maintaining each programmable logic circuit within an operation range at a minimum voltage

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Kanagawa-ken, Japan

Yukimasa Miyamoto